Battery pack having a processor controlled battery operating system

• US 5,646,508 A
• Filed: 06/07/1995
• Issued: 07/08/1997
• Est. Priority Date: 11/10/1994
• Status: Expired due to Fees

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Duracell Incorporated (Berkshire Hathaway Incorporated)
• Inventors: Friel, Daniel D., Hull, Matthew P., Taylor, Alwyn H., Wieczorek, Rudi, van Phuoc, Duong, Zeising, Elmar, Hruska, Louis W.
• Primary Examiner(s): Nappi, Robert
• Assistant Examiner(s): TOATLEY, GREGORY J
• Application Number:
  US08/486,071
• Time in Patent Office: 762 Days
• Field of Search: 320/5, 320/19, 320/20, 320/22, 320/30, 320/35, 320/48, 324/426, 365/96, 365/106
• US Class Current: 320/152
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
• CPC Class Codes: H01M 10/42 Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells H01M10/60 takes precedence
• CPC Class Codes: H01M 10/4257 Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
• CPC Class Codes: H01M 10/44 Methods for charging or discharging circuits for charging H02J7/00
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H01M 6/5011 for several cells simultaneously or successively
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/00036 Charger exchanging data with battery
• CPC Class Codes: H02J 7/00047 with provisions for charging different types of batteries
• CPC Class Codes: H02J 9/061 for DC powered loads
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y10S 320/13 Fault detection

Abstract

A rechargeable battery pack and a method of operating a rechargeable battery system. The battery pack includes a rechargeable battery, a processor for monitoring operation and performance of the battery, and a memory area for storing data values used by the processor. The memory area is normally powered by the battery, and a capacitor is provided to supply back-up power to the memory area in case of an interruption in the supply of electrical power to the memory area from the battery. The battery pack further includes a delatching circuit for electronically decoupling the memory area and the back-up capacitor from the battery under predetermined conditions.

Claims

1. A smart battery having a power management system capable of self powered operation, even if accidently shorted, said smart battery comprising:

(a) a plurality of rechargeable cells connected to positive and negative terminals to provide electrical power to an external device during a discharge mode and to receive electrical power during a charge mode, as provided or determined by said remote device, said battery including a separate voltage tap between said pair of terminals for defining a digital voltage source and a fuse between said tap and said positive terminal;

(b) a positive thermal coefficient device mounted in series with said cells and said terminals, said device having a conductive state for normal operation and a non-conductive state for momentarily interrupting current flow between said cells and said terminals in the event of a short;

(c) an analog means for generating analog signals representative of battery voltage and current at said terminals;

(d) a hybrid integrated circuit (IC) having an analog to digital convertor and a microprocessor for receiving the analog signals and converting them to digital signals representative of battery voltage, current and temperature, and calculating actual charge parameters over time from said digital signals, said charge parameters including at least a learned full charge capacity and remaining capacity;

(e) a data memory defined within said hybrid IC for storing said actual charge parameters, even when said battery is nominally fully discharged;

(f) means for supplying electrical power to the data memory from said voltage tap;

(g) a capacitor also electrically connected to the voltage tap for receiving electrical power therefrom, and for supplying power to said data memory in the event the supply of power to the data memory from the voltage tap is interrupted;

whereby said memory is momentarily powered by said capacitor in the event of a short, until the short is removed or said fuse interrupts current flow to said positive terminal, said voltage tap providing power for said data memory after said positive thermal coefficient device has returned to a conductive state; and

(h) a delatching circuit for electrically decoupling both the memory area and the capacitor from the voltage tap under predetermined conditions.

2. A battery pack comprising:

terminal means for connecting the battery pack to a battery powered device and to a battery recharger;

a battery including at least one rechargeable battery cell connected to the terminal means, said battery having

i) a discharge mode for supplying electrical power to the battery powered device, and

ii) a charge mode for receiving electrical power from the terminal means;

means to sense and to generate signals representing battery voltage, battery temperature or battery current;

a processor for receiving the signals representing battery voltage, battery temperature or battery current, and for performing a predefined series of calculations using said signals;

a memory area for storing data values including at least values representing at least one of battery voltage, battery temperature and battery current;

a power supply circuit electrically connecting the memory area to the battery to supply electrical power to the memory area from the battery, and including

i) a capacitor to receive electrical power from the battery and to supply electrical power to the memory area in case of an interruption in the supply of electrical power from the battery, and

ii) a delatching subcircuit for electrically decoupling both the memory area and the capacitor from the battery under predetermined conditions.

3. A battery pack according to claim 2, further including an internal power terminal;

and wherein the power supply circuit includes;

means electrically connecting the battery to said power terminal to supply electrical power to said power terminal from the battery; and

means electrically connecting the power terminal to the memory area to supply electrical power to said memory area from the power terminal.

4. A battery pack according to claim 3, wherein the delatching circuit electrically decouples the memory area from the power terminal when the voltage of the power terminal falls below a given level.

5. A battery pack according to claim 4, wherein:

the delatching circuit includes

i) a switching transistor located in the means electrically connecting the power terminal to the memory area,

ii) a sensor for sensing, and for generating a signal representing, the voltage of the power terminal, and

iii) means for applying to the switching transistor the signal representing the voltage of the power terminal;

the switching transistor has

i) a conductive state for electrically coupling the memory area to the power terminal, and

ii) a non-conductive state for electrically decoupling said memory area from the power terminal; and

the switching transistor switches from the conductive state to the non-conductive state when the voltage of the power terminal falls below the given level.

6. A battery pack according to claim 2, wherein the terminal means includes first and second terminals and wherein the battery pack further includes means to inhibit the flow of current through the battery in case of a short circuit across the first and second terminal, and to help maintain the flow of current from the battery to the memory area in case of said short circuit.

7. A battery pack according to claim 6, wherein the means to inhibit the flow of current through the battery includes a fuse located in series between the battery cell and one of the terminals.

8. A battery pack according to claim 6, wherein the means to inhibit the flow of current through the battery includes a positive temperature coefficient element located in series between the battery cell and one of the terminals, for creating a high impedance between the battery cell and said one of the terminals in case of said short circuit.

9. A battery pack according to claim 6, wherein:

in case of an interruption of the supply of electrical power to the memory area from the battery, said memory area receives electrical power from the capacitor for at least a given period of time; and

in case of a short circuit across the first and second terminals, the means to inhibit the flow of current through the battery raises the voltage of the battery above said preset level within said given period of time.

10. A battery according to claim 2, wherein:

the battery has a variable capacity; and

said series of calculations include

i) calculating a value representing remaining capacity of the battery, and

ii) calculating a value representing learned capacity of the battery.

11. A method of operating a battery system having a rechargeable battery, a processor and a memory area, the method comprising:

sensing, and generating signals representing, battery voltage, battery temperature or battery current;

storing data values in the memory area, said stored data values including at least values representing at least one of battery voltage, battery temperature and battery current;

the processor performing a series of predefined calculations using said data values;

supplying electrical power to the memory area from the battery;

also supplying electrical power to a capacitor from the battery to develop an electric voltage level in the capacitor;

supplying electrical power to the memory area from the capacitor in case of an interruption in the supply of electrical power to the memory area from the battery; and

electrically decoupling both the memory area and the capacitor from the battery under predetermined conditions.

12. A method according to claim 11, wherein the step of supplying electrical power from the battery to the memory area includes the step of conducting electrical current from the battery to the memory area via a power supply circuit.

13. A method according to claim 12, wherein the step of electrically decoupling the memory area from the battery includes the steps of:

sensing voltage in the power supply circuit; and

electrically decoupling the memory area from the battery when the sensed voltage in the power supply circuit falls below a given level.

14. A method according to claim 13, wherein the battery system includes an integrated circuit, the processor and the memory area are part of the integrated circuit, and the integrated circuit further includes a power terminal, and wherein the step of conducting electrical current from the battery to the memory area includes the steps of:

electrically coupling the power terminal to the battery to produce a voltage level at the power terminal; and

electrically coupling the power terminal to the memory area to apply to said memory area the voltage level at the power terminal.

15. A method according to claim 14, wherein:

the step of sensing voltage in the power supply circuit includes the step of sensing the voltage level at said power terminal; and

the step of decoupling the memory area from the battery when the sensed voltage in the power supply circuit falls below a given voltage level includes the step of electrically decoupling the memory area from the power terminal when the voltage level at said power terminal falls below the given level.

16. A method according to claim 11, wherein the battery system further includes first and second terminals and the rechargeable battery is connected to said terminals to supply electrical power to a battery powered device, and wherein the method further includes the step of

inhibiting the flow of current through the battery in case of a short circuit across the first and second terminals to help maintain the flow of current from the battery to the memory area in case of said short circuit.

17. A method according to claim 16, wherein:

the step of inhibiting the flow of current through the battery includes the step of raising the voltage of the battery above said predetermined voltage level within a given period of time; and

the step of supplying electrical power to the memory area from the capacitor includes the step of, in case of said short circuit, conducting electrical power from the capacitor to the memory area to maintain a voltage level at the memory area above a predetermined voltage level for at least a given period of time.

18. A method according to claim 11, wherein the battery has a nominally fully discharged voltage value, and the memory area requires a minimum operating voltage to maintain said stored data values, said minimum operating voltage being below said nominally fully discharged voltage, and wherein the method further comprises the step of

when the battery voltage is below the nominally fully discharged voltage value, applying a voltage to the memory area that is above said minimum operating voltage to maintain said stored data values.