Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device

• US 5,646,900 A
• Filed: 01/11/1996
• Issued: 07/08/1997
• Est. Priority Date: 01/12/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tsukude, Masaki, Arimoto, Kazutami
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/583,893
• Time in Patent Office: 544 Days
• Field of Search: 365/205, 365/207, 365/208, 365/189.09, 365/190, 365/227, 365/203, 365/193, 365/194
• US Class Current: 365/205
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

N channel sense amplifier transistors have their backgate potentials set to a backgate precharge potential higher than a potential intermediate between an operation power supply potential and a ground potential prior to start of sensing operation, and then lowered following the lowering of an n common source node potential during the sensing operation. The n common source node is precharged to the intermediate potential. The backgate precharge potential is set no greater than a potential of the intermediate potential plus a pn junction diffusion, to suppress a leakage current from the backgate to source or drain of each of the sense amplifier transistors. P channel sense amplifier transistors have also their backgate potential set to a precharge potential lower than the intermediate potential prior to sensing operation and raised following the rise of a p common source node potential.

Claims

1. A sense amplifier circuit for differentially amplifying potentials on a first bit line and a second bit line paired with said first bit line, said first and second bit lines precharged at an intermediate potential between a first power potential and a second power potential different from said first power potential, said sense amplifier circuit comprising:

a first activation transistor coupled between a first power node receiving said first power potential and a first node precharged to said intermediate potential and responsive to a first sense amplifier enable signal being active for electrically coupling said first power node and said first node;

a first sense transistor connected between said first node and said first bit line and having a gate coupled to said second bit line and having a backgate receiving a first backgate potential precharged to a first precharge potential prior to activation of said first sense amplifier enable signal and changing with a potential at said first node during activation of said first sense amplifier enable signal, a difference in absolute value between said first precharge potential and said first power potential being greater than that between said intermediate potential and said first power potential; and

a second sense transistor connected between said first node and said second bit line and having a gate coupled to said first bit line and a backgate receiving said first backgate potential.

2. The sense amplifier circuit according to claim 1, wherein each of said first and second sense transistors comprises a first impurity region of a first conductivity type electrically connected to a corresponding one of the first and second bit lines, a second impurity region of said first conductivity type spaced apart from said first impurity region and electrically connected to said first node, and a bulk region of a second conductivity type different from said first conductivity type and serving as said backgate, and wherein a difference in absolute value between said first precharge potential and said intermediate potential is no greater than a pn junction diffusion potential at a junction between said first and second impurity regions and said bulk region.

3. The sense amplifier circuit according to claim 2, wherein one of said first and second bit lines has a potential changed by a read out voltage due to reading out of memory cell data during precharging of said backgate to said first precharge potential, and wherein said first precharged potential is set to such a potential level that said difference in absolute value is greater than zero and no greater than a value of said pn junction diffusion potential minus said read out voltage.

4. The sense amplifier circuit according to claim 1, wherein said first and second sense transistors each comprise a p channel insulated gate type transistor, and said first power potential is an operational power supply potential for said sense amplifier circuit, and said second power potential is a ground potential for said sense amplifier circuit.

5. The sense amplifier circuit according to claim 1, wherein said first and second sense transistors each comprise an n channel insulated gate type transistor, and said first power potential is a ground potential for said sense amplifier circuit, and said second power potential is an operation power supply potential for said sense amplifier circuit.

6. The sense amplifier circuit according to claim 5, wherein said first precharge potential is the operation power supply potential for said sense amplifier circuit.

7. The sense amplifier circuit according to claim 4, wherein said first precharge potential is the ground potential for said sense amplifier circuit.

8. The sense amplifier circuit according to claim 1, wherein said first and second sense transistors are formed on an SOI substrate having an insulation layer formed on a semiconductor region.

9. The sense amplifier circuit according to claim 1, further comprising:

a second activation transistor coupled between a second power node receiving said second power potential and a second node precharged to said intermediate potential and responsive to a second sense amplifier enable signal being active for electrically coupling said second power node and said second node;

a third sense transistor connected between said second node and said first bit line and having a gate coupled to said second bit line and having a second backgate receiving a second backgate potential precharged to a second precharge potential prior to activation of said second sense amplifier enable signal and changing with a potential at said second node during activation of said second sense amplifier enable signal, a difference in absolute value between said second precharge potential and said second power potential being greater than that between said intermediate potential and said second power potential; and

a fourth sense transistor connected between said second node and said second bit line and having a gate coupled to said first bit line and a second backgate receiving said second backgate potential.

10. The sense amplifier circuit according to claim 9, wherein each of said third and fourth sense transistors comprises a third impurity region of a second conductivity type electrically connected to a corresponding one of the first and second bit lines, a fourth impurity region of said second conductivity type spaced apart from said third impurity region and electrically connected to said second node, and a second bulk region of a first conductivity type different from said second conductivity type and serving as said second backgate, and wherein a difference in absolute value between said second precharge potential and said intermediate potential is no greater than a pn junction diffusion potential at a junction between said third and fourth impurity regions and said second bulk region.

11. The sense amplifier circuit according to claim 10, wherein one of said first and second bit liens has a potential changed by a read out voltage due to reading out of memory cell data during precharging of said second backgate to said second precharge potential, and wherein said second precharge potential is set to such a potential level that said difference in absolute value is greater than zero and no greater than a value of said pn junction diffusion potential minus said read out voltage.

12. The sense amplifier circuit according to claim 9, wherein said third and fourth sense transistors each comprise a p channel insulated gate type transistor, and said second power potential is an operational power supply potential for said sense amplifier circuit, and said first power potential is a ground potential for said sense amplifier circuit.

13. The sense amplifier circuit according to claim 9, wherein said third and fourth sense transistors each comprise an n channel insulated gate type transistor and said second power potential is a ground potential for said sense amplifier circuit, and said first power potential is an operation power supply potential for said sense amplifier circuit.

14. The sense amplifier circuit according to claim 13, wherein said second precharge potential is the operation power supply potential for said sense amplifier circuit.

15. The sense amplifier circuit according to claim 12, wherein said second precharge potential is the ground potential for said sense amplifier circuit.

16. The sense amplifier circuit according to claim 9, wherein said third and fourth sense transistors are formed on an SOI substrate having an insulation layer formed on a semiconductor region.

17. A semiconductor memory device comprising:

a first and second bit lines each connecting a predetermined number of memory cells;

a sense amplifier including a first sense transistor coupled between a first node and said first bit line and having a control gate coupled to said second bit line and a first backgate, and a second sense transistor coupled between said first node and said second bit line and having a control gate coupled to said first bit line and a second backgate, said first and second backgates connected to a first backgate node, for differentially amplifying potentials on said first and second bit lines;

a first sense enable transistor coupled between a first power node and said first node and responsive to a first sense amplifier enable signal being active for electrically connecting said first power node and said first node;

precharge circuitry coupled to said first node for precharging said first node at an intermediate potential between a first power potential and a second power potential different from said first power potential in response to a precharge instructing signal being active;

first backgate potential generator operating with said first and second power potentials for generating a first backgate precharge potential at a level between said intermediate potential and said second power potential;

a first means coupled between said first backgate potential generator and said first backgate node for transmitting said first backgate precharge potential onto said first backgate node in response to a first control signal being active;

a second means coupled between said first node and said first backgate node for electrically connecting said first node and said first backgate node in response to a second control signal being active; and

controller coupled to receive a memory cycle start instructing signal and responsive to activation of said memory cycle start instructing signal for activating said first control signal for application to said first means prior to activation of said first sense amplifier enable signal, and for activating said second control signal during activation of said first sense amplifier enable signal, said precharge instructing signal being deactivated in response to activation of said memory cycle start instruct signal, and said first sense amplifier enable signal being activated in response to the activation of said memory cycle start instructing signal.

18. The semiconductor memory device according to claim 17, wherein said controller includes;

a first delay means coupled to receive said memory cycle start instructing signal for delaying said memory cycle start instructing signal by a first predetermined time to generate a third control signal,

a first gate means coupled to receive said third control signal for activating said first control signal for a second predetermined time in response to deactivation of said third control signal, and

a second gate means coupled to receive said first and third control signals for activating said second control signal in response to deactivation of both of said first and third control signals.

19. The semiconductor memory device according to claim 18, further comprising

a third means coupled between said first power node and said first backgate node and responsive to said third control signal being active for electrically connecting said first power node and said first backgate node.

20. The semiconductor memory device according to claim 18, wherein each of said first and second sense transistors comprises a first impurity region of a first conductivity type electrically connected to a corresponding one of the first and second bit lines, a second impurity region of said first conductivity type spaced apart from said first impurity region and electrically connected to said first node, and a bulk region of a second conductivity type different from said first conductivity type and serving as said backgate, and wherein a difference in absolute value between said first backgate precharge potential and said intermediate potential is no greater than a pn junction diffusion potential at a junction between said first and second impurity regions and said bulk region.

21. The semiconductor memory device according to claim 20, wherein one of said first and second bit lines has a potential changed by a read out voltage due to reading out of memory cell data prior to activation of said first control signal and wherein said first backgate precharge potential is set to such a potential level that said difference in absolute value is greater than zero and no greater than a value of said pn junction diffusion potential minus said read out voltage.

22. The semiconductor memory device according to claim 17, wherein said first and second sense transistors each comprise a p channel insulated gate type transistor, and said first power potential is an operational power supply potential, and said second power potential is a ground potential, and said first backgate precharge potential is the ground potential.

23. The semiconductor memory device according to claim 17, wherein said first and second sense transistors each comprise an n channel insulated gate type transistor, and said first power potential is a ground potential, and said second power potential is an operation power supply potential, and said first backgate precharge potential is the operation power supply potential.

24. The semiconductor memory device according to claim 17, wherein said first and second sense transistors are formed on an SOI substrate having an insulation layer formed on a semiconductor region.

25. The semiconductor memory device according to claim 17, wherein said sense amplifier further includes a third sense transistor coupled between a second node and said first bit line and having a control gate coupled to said second bit line and a third backgate, and a fourth sense transistor coupled between said second node and said second bit line and having a control gate coupled to said first bit line and a fourth backgate, said third and fourth backgates connected to a second backgate node, and

said precharge circuitry includes means coupled to said second node to precharge said second node to said intermediate potential in response to said precharge instructing signal being active, and wherein said semiconductor memory device further comprises,

second backgate potential generator operating with said first and second power potentials for generating a second backgate precharge potential at a level between said intermediate level and said first power potential,

a first connecting means coupled between said second backgate potential generator and said second backgate node for transmitting said second backgate precharge potential onto said second backgate node in response to said first control signal being active;

a second connecting means coupled between said second node and said second backgate node for electrically connecting said second node and said second backgate node in response to said second control signal being active,

a second sense enable transistor coupled between a second power node receiving said second power potential and responsive to a second sense amplifier enable signal for coupling said second node to said second power node.

26. The semiconductor memory device according to claim 25, further comprising

means coupled between said second power node and said second backgate node for electrically connecting said second power node and said second backgate node in response to deactivation of said memory cycle start instruct signal.

27. The semiconductor memory device according to claim 25, wherein each of said third and fourth sense transistors comprise a third impurity region of a second conductivity type electrically connected to a corresponding one of the first and second bit lines, a fourth impurity region of said second conductivity type spaced apart from said third impurity region and electrically connected to said second node, and a second bulk region of a first conductivity type different from said second conductivity type and serving as said third or fourth backgate, and wherein a difference in absolute value between said second precharge potential and said intermediate potential is no greater than a pn junction diffusion potential at a junction between said third and fourth impurity regions and said second bulk region.

28. The semiconductor memory device according to claim 27, wherein one of said first and second bit lines has a potential changed by a read out voltage due to reading out of memory cell data, and wherein said second precharge potential is set to such a potential level that said difference in absolute value is greater than zero and no greater than a value of said pn junction diffusion potential minus said read out voltage.

29. The semiconductor memory device according to claim 25, wherein said third and fourth sense transistors each comprise a p channel insulated gate type transistor, and said second power potential is an operation power supply potential, and said first power potential and said second backgate precharge potential each are a ground potential.

30. The semiconductor memory device according to claim 25, wherein said third and fourth sense transistors each comprise an n channel insulated gate type transistor, and said first power potential and said second backgate precharge potential each are an operation power supply potential, and said second power potential is a ground potential.

31. The semiconductor memory device according to claim 25, wherein said third and fourth sense transistors are formed on an SOI substrate having an insulation layer formed on a semiconductor region.