High speed flash memory cell structure and method

• US 5,648,669 A
• Filed: 05/26/1995
• Issued: 07/15/1997
• Est. Priority Date: 05/26/1995
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Norris, Christopher S., Sethi, Rakesh Balraj, Hu, Genda J.
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/452,217
• Time in Patent Office: 781 Days
• Field of Search: 257/316, 257/317, 257/318, 257/319, 257/320, 257/321, 257/322
• US Class Current: 257/318
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts. The erase node includes a buried N+ drain region in a P-type substrate, a buried implant plate doped N-type adjacent the drain region in the substrate, a tunnel oxide disposed over at least a portion of the plate and the drain region, the tunnel oxide extending into and abutting a gate oxide region, and thence to a field oxide region in a relaxed fashion, a polycrystalline silicon floating gate disposed over the field oxide, gate oxide, and tunnel oxide regions, a sandwich of ONO on the floating gate, and a polycrystalline silicon control gate (poly 2) disposed on the ONO. Programming occurs through the programming transistor. Reading occurs through a read path including the read transistor. During programming, coupling is improved at the gate of the programming transistor by an erase node boosting technique. This technique involves applying a relatively "boosted" voltage level to the drain region of the erase node which reduces the backbias threshold effect of erase node capacitors. Similarly, during a read operation, a relatively "boosted" voltage is applied to the drain region of the erase node, which, by way of the buried implant plate, reduces the backbias threshold effect of the erase node capacitors wherein coupling at the control gate of the read transistor is improved.

Claims

1. A memory cell for storing binary data having two possible states suitable for use in a programmable logic array (PLA), comprising:

EPROM read means for determining said state of said cell, said EPROM read means including an EPROM read transistor having a floating gate chargeable to correspond to one of said two states and a control gate coupled to an input term, said EPROM read transistor having first source and drain regions forming a first channel therebetween;

an erase node coupled with an erase line sharing said floating gate and said control gate with said EPROM read transistor for erasing said cell by removing charge from said floating gate through a tunnel dielectric, said erase node further including means proximate said tunnel dielectric for reducing a backbias threshold effect;

said backbias reducing means being responsive to a first signal on said erase line during a programming mode to improve program coupling,

said backbias reducing means being responsive to a second signal on said erase line during a read mode to improve read coupling.

2. The memory cell of claim 1 wherein said EPROM read means further includes a low voltage pass gate transistor having second source and drain regions forming a second channel therebetween, said second drain being coupled to said first source to thereby connect said first and second channels wherein a read product term is coupled to one of said first drain and second source for causing a current to flow through said first and second channels that is indicative of one of said states of said memory, cell,

said floating gate and said control gate comprising polycrystalline silicon material.

3. The memory cell of claim 2 further comprising:

an EPROM program transistor sharing said floating gate and said control gate with said erase node for charging said floating gate during said programming mode to thereby alter said state of said memory cell,

wherein programming of said cell occurs through said EPROM program transistor and reading of said cell occurs through said EPROM read means to thereby isolate program and read paths for speed optimization.

4. The memory cell of claim 3 wherein said EPROM program transistor has third source and drain regions forming a third channel therebetween, said cell further comprising:

a program select transistor having fourth source and drain regions forming a fourth channel therebetween, said third drain being coupled to said fourth source to thereby connect said third and fourth channels, said program select transistor being responsive to a pass gate select signal for selectively activating said third and fourth channels to carry current for programming said cell.

5. The memory cell of claim 2 further comprising:

a program and erase transistor coupled to said erase node for programming said cell through said tunnel oxide, and for erasing said cell through of said tunnel oxide.

6. An electrically-erasable, EPROM-type programmable memory cell for storing binary data having two possible states suitable for use in a programmable logic array (PLA) having an input term and a read product term, comprising:

an EPROM read transistor having a floating gate chargeable to correspond to one of said states and a control gate coupled to said input term, said EPROM read transistor having first source and drain regions forming a first channel therebetween, said floating gate and said control gate comprising polycrystalline silicon material;

a low voltage pass gate transistor having second source and drain regions forming a second channel therebetween, said second drain being coupled to said first source to thereby connect said first and second channels to form a read path wherein said read product term is coupled to one of said first drain and second source for causing a current to flow through said first and second channels during a read mode indicative of one of said states said memory cell;

an EPROM program transistor sharing said floating gate and said control gate with said EPROM read transistor for charging said floating gate during a programming mode to thereby alter said state of said memory cell,

an erase node coupled to an erase like sharing said floating gate and said control gate for erasing said cell by removing charge from said floating gate through a tunnel dielectric associated therewith, said erase node further including a buried implant plate proximate said tunnel dielectric for reducing a backbias threshold effect;

said implant plate being responsive to a first signal on said erase line during said programming mode to improve program coupling,

said implant plate being responsive to a second signal on said erase line during said read mode to improve read coupling, and,

whereby programming of said cell occurs through said EPROM program transistor and reading of said cell occurs through said EPROM read means to thereby isolate program and read paths for speed optimization.

7. The memory cell of claim 6 wherein said tunnel dielectric is formed adjacent a floating gate dielectric.

8. The memory cell of claim 6 wherein said runnel dielectric is formed adjacent a field dielectric.