High speed flash memory cell structure and method

  • US 5,648,669 A
  • Filed: 05/26/1995
  • Issued: 07/15/1997
  • Est. Priority Date: 05/26/1995
  • Status: Expired due to Term
First Claim
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1. A memory cell for storing binary data having two possible states suitable for use in a programmable logic array (PLA), comprising:

  • EPROM read means for determining said state of said cell, said EPROM read means including an EPROM read transistor having a floating gate chargeable to correspond to one of said two states and a control gate coupled to an input term, said EPROM read transistor having first source and drain regions forming a first channel therebetween;

    an erase node coupled with an erase line sharing said floating gate and said control gate with said EPROM read transistor for erasing said cell by removing charge from said floating gate through a tunnel dielectric, said erase node further including means proximate said tunnel dielectric for reducing a backbias threshold effect;

    said backbias reducing means being responsive to a first signal on said erase line during a programming mode to improve program coupling,said backbias reducing means being responsive to a second signal on said erase line during a read mode to improve read coupling.

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