Reduced noise semiconductor package stack

• US 5,656,856 A
• Filed: 06/07/1995
• Issued: 08/12/1997
• Est. Priority Date: 06/09/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kweon, Young Do
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): ARROYO, TERESA M
• Application Number:
  US08/487,323
• Time in Patent Office: 797 Days
• Field of Search: 257/685, 257/686, 257/723, 257/777
• US Class Current: 257/686
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 24/01 Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor package stack assembly providing reduced electrical noise, in which a conductive film is provided on an exposed bottom surface of the semiconductor chip of each semiconductor package in a unitary stack thereof, each conductive film being grounded to ground lines of the printed circuit board on which the lowermost package of the stack is surface-mounted.

Claims

1. A semiconductor package stack providing reduced electrical noise, comprising:

a plurality of semiconductor packages, each package being stacked one upon another in a single stack having a lowermost said package, each said package having a semiconductor chip having a plurality of bonding pads, a plurality of inner and outer leads, an insulating film of film carrier, which mounts said chip by electrically connecting said bonding pads thereof to corresponding ones of said inner leads by bumps, and a molded-in-place covering which protects the chip and inner leads from the external environment, said chip having an exposed bottom surface;

a plurality of frames each having a top surface and a bottom surface, each said frame being formed so as to have circuit patterns on the top and bottom surfaces thereof, said frames being alternating interspersed with said packages in said stack, with a frame lowermost, said circuit patterns being electrically connected to respective ones of the outer leads to unite the semiconductor packages into a stack;

a substrate formed so as to have ground land patterns, said ground land patterns being electrically commonly connected to said circuit patterns on respective ones of said frames;

an electrically conductive film formed on the exposed bottom surface of the chip of each said package, said electrically conductive film being effectively connected to said inner leads; and

a plurality of ground terminals, which are electrically connected to said conductive film as well as to said ground land patterns formed on said substrate.

2. The semiconductor package stack of claim 1, wherein:

said conductive film is made of a metal selected from the group consisting of copper, gold, silver, aluminum, tin, and alloys thereof.

3. The semiconductor package stack of claim 1, wherein:

said ground terminals are made of a metal selected from the group consisting of copper, gold, silver, aluminum, tin, and alloys thereof.

4. The semiconductor package stack of claim 1, wherein:

said ground terminals are electrically connected to respective ones of said outer leads.

5. The semiconductor package stack of claim 1, wherein:

said frames have edges and said ground terminals are located at said edges of said frames.

6. The semiconductor package stack of claim 1, further comprising:

at least one capacitor for reducing electrical noise, each said capacitor being formed onto a land pattern formed on an area of the substrate located directly beneath the exposed bottom surface of the chip.

7. A semiconductor package stack providing reduced electrical noise comprising:

a plurality of semiconductor packages, each package being stacked one upon another in a single stack having a lowermost said package, each said package having a semiconductor chip having a plurality of bonding pads, a plurality of inner and outer leads, an insulating film of film carrier, which mounts said chip by electrically connecting said bonding pads thereof to corresponding ones of said inner leads by bumps, and a molded-in-place covering which protects the chip and inner leads from the external environment, said chip having an exposed bottom surface;

a plurality of frames each having a top surface and a bottom surface, each said frame being formed so as to have circuit patterns on the top and bottom surfaces thereof, said frames being alternating interspersed with said packages in said stack, with a frame lowermost, said circuit patterns being electrically connected to respective ones of the outer leads to unite the semiconductor packages into a stack;

a substrate formed so as to have ground land patterns, said ground land patterns being electrically commonly connected to said circuit patterns on respective ones of said frames;

an electrically conductive film formed on the exposed bottom surface of the chip of each said package, so as to have an outer surface, said electrically conductive film being effectively connected to said inner leads;

an insulating film formed on said surface of the conductive film; and

a plurality of ground terminals, which are electrically connected to said conductive film as well as to said ground land patterns formed on said substrate.

8. The semiconductor package stack of claim 7, wherein:

said lowermost package is formed so as to provide said insulating film and conductive film consecutively on the exposed bottom surface of the chip thereof.

9. The semiconductor package stack of claim 7, wherein:

said frames have edges and said ground terminals are located on said edges of said frame of said lowermost package.

10. The semiconductor package stack of claim 7, wherein:

said ground terminals are electrically connected to corresponding ones of said outer leads except for those of said lowermost package.

11. The semiconductor package stack of claim 7, further comprising:

at least one capacitor for reducing electrical noise, each said capacitor being formed onto a land pattern formed on an area of the substrate located directly beneath the exposed bottom surface of the chip.

12. The semiconductor package stack of claim 7, wherein:

said conductive film is made of a metal selected from the group consisting of copper, gold, silver, aluminum, tin, and alloys thereof.

13. The semiconductor package stack of claim 7, wherein:

said ground terminals are made of a metal selected from the group consisting of copper, gold, silver, aluminum, tin, and alloys thereof.

14. A semiconductor package stack providing reduced electrical noise, comprising:

a plurality of semiconductor packages, each package being stacked one upon another in a single stack having a lowermost said package, each said package having a semiconductor chip having a plurality of bonding pads, and a plurality inner and outer leads electrically connected to the corresponding bonding pads by bumps to mount the respective chip;

a cap formed so as to have conductive layers on inner opposite side surfaces thereof, said conductive layers commonly electrically connecting respective outer leads of each package together to unite the semiconductor packages;

a substrate formed so as to have land patterns, said land patterns being electrically connected to respective ones of said outer leads via said conductive layers of said cap;

each said package having;

an electrically conductive film formed on a bottom surface of the chip thereof, said electrically conductive film being effectively connected to said inner leads;

an insulating film formed on a surface of the conductive film; and

a plurality of ground terminals, which are electrically connected to the conductive film and to said ground land patterns formed on the substrate.

15. The semiconductor package stack of claim 14, wherein:

said conductive film is made of a metal selected from the group consisting of copper, gold, silver, aluminum, tin, and alloys thereof.

16. The semiconductor package stack of claim 14, wherein:

said ground terminals are made of a metal selected from the group consisting of copper, gold, silver, aluminum, tin, and alloys thereof.