Method for the anticipated reading of serial access memory, and memory pertaining thereto

• US 5,663,922 A
• Filed: 11/03/1995
• Issued: 09/02/1997
• Est. Priority Date: 11/10/1994
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Tailliet, Fran.cedilla.ois
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/552,996
• Time in Patent Office: 669 Days
• Field of Search: 365/221, 365/189.02, 365/189.12, 365/230.03, 365/236, 365/239, 365/240, 365/184
• US Class Current: 365/240
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A method and apparatus for reading a memory, such that the address decoding is started when the address bits have not yet all been received. All the information elements corresponding to the partially decoded address are extracted and, when the last address bits have been received, the information element corresponding to the complete address is selected. The maximum permissible time for extracting an information element is thus increased internally, while this period of time external to the memory remains the same for a given frequency.

Claims

1. A method of reading the contents of words of a memory in integrated circuit form, each memory being organized in matrix form in words, the contents of each word representing a binary information element, each word being accessible at a particular address encoded in binary mode on k bits, k being an integer greater than 1, the address bits being received in series by the memory at an address input terminal, comprising the steps of:

serially receiving q first bits of the address of the word to be read, with q as an integer smaller than k;

in parallel with the reception of k-q last bits of the address;

decoding the q first bits of the address that are received and connecting read circuits to the words for which the q first address bits correspond to the q first address bits received;

extracting the binary information elements represented by the contents of the words for which the q first address bits correspond to the q first address bits received; and

decoding the k-q last bits of the address of the word to be read and supplying, at a data output terminal of the memory, the binary information element that is represented by the contents of the word whose address bits correspond to the k address bits received.

2. A method according to claim 1, wherein the memory has a sequential read mode such that, following the step of reading the contents of a first word corresponding to a first address, the memory automatically provides a second binary information element at the data output terminal, this second binary information element being represented by the contents of a second word of the memory.

3. A method according to claim 2, wherein the decoding of the address of the second word takes place during the step of supplying, at the data output terminal, the binary information represented by the contents of the first word.

4. A method according to claim 2 wherein, in sequential read mode, one binary information element at a time is extracted.

5. A memory in integrated circuit form organized in words, the contents of each word representing a binary information element, each word being accessible at a particular address encoded in binary mode on k bits, k being an integer greater than 1, the memory comprising:

an address input terminal to receive the address bits in series,

a data output terminal to provide the binary information elements corresponding to the contents of the addressed words,

an input register coupled to the address input terminal to store received address bits received at the address input terminal,

decoding circuits coupled to the input register for decoding the received address bits, and

circuits coupled to read circuits and said decoding circuits for connecting the words to said read circuits, wherein

the words are organized in groups of words in such a way that the words in each group have k-q identical last address bits, with q as an integer smaller than k, and q first distinct address bits,

each group of words has an associated read circuit so that, when the memory receives k address bits, the memory extracts the binary information that is represented by the contents of the word of the group corresponding to the q first address bits received, and

the memory further comprises control and output multiplexing circuits coupled to said read circuits and said data output terminal to supply, at the data output terminal, the binary information that is represented by the contents of the word whose address corresponds to the k bits received.

6. A memory according to claim 5, wherein the input register is formed by two shift sub-registers respectively formed by q and k-q cells.

7. A memory according to claim 6, wherein the input register is a binary address counter.

8. A memory according to claim 7, wherein the control circuit comprises means for modifying the contents of the input register.

9. A memory according to claim 5, further comprising an output register connected to the read circuits in order to store the binary information elements extracted by these read circuits.

10. A memory according to claim 5, wherein the memory is an electrically programmable and erasable memory.

11. A memory for storing a plurality of words, each word having an address of k bits associated therewith, the memory comprising:

a first memory array for storing a first group of words of said plurality of words;

a second memory array for storing a second group of words of said plurality of words, wherein for each word in the first group of words there is a corresponding word in the second group of words having a same k minus q address bits associated therewith;

a first read circuit coupled to the first memory array, for reading a first word having a first address associated therewith from the first memory array; and

a second read circuit coupled to the second memory array for reading a second word from the second memory array substantially simultaneousl read by the first read circuit, the second word having the second address having the same k minus q address bits associated therewith as the first address.

12. The memory of claim 11, further comprising an input register for serially receiving an address of a word to be read from the memory.

13. The memory of claim 12, wherein the input register is a shift register, comprising a first subregister that has a capacity to hold q bits and a second subregister that has a capacity to hold k minus q bits.

14. The memory of claim 13, further comprising a multiplexer coupled to the first and second read circuits and an output register coupled to the multiplexor.

15. The memory of claim 14, further comprising a control circuit coupled to the second subregister, the multiplexor and the first and second read circuits, the control circuit for receiving the k minus q bits from the second subregister.

16. The memory of claim 12, wherein the input register is a binary address counter, having a first subregister that has a capacity to hold q bits and a second subregister that has a capacity to hold k minus q bits.

17. The memory of claim 16, further comprising a multiplexer coupled to the first and second read circuits and an output register coupled to the multiplexor.

18. The memory of claim 17, further comprising a control circuit coupled to the second subregister, the multiplexor and the first and second read circuits, the control circuit for receiving the k minus q bits from the second subregister, and controlling the binary address counter to increment its contents.

19. A method of reading a binary word having a k bit address associated therewith from a memory, comprising the steps of:

(A) decoding q first address bits;

(B) reading every word from the memory having a same first q address bits associated therewith; and

(C) selecting a word read in step (B) having k minus q address bits corresponding the binary word.

20. The method of claim 19, wherein step (C) includes decoding the last k-q address bits.

21. The method of claim 20, further comprising selecting a word having a same address as the word selected in step (C) incremented by one.

22. The method of claim 19, further comprising storing the k bit address in a register before step (A) occurs.

23. The method of claim 22, further comprising incrementing the contents of the register by one and selecting a word having a same address as the word selected in step (C) incremented by one.