Process for creating high density integrated circuits utilizing double coating photoresist mask

• US 5,667,940 A
• Filed: 11/06/1996
• Issued: 09/16/1997
• Est. Priority Date: 05/11/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsue, Chen-Chiu, Hong, Gary
• Primary Examiner(s): Young, Christopher G.
• Application Number:
  US08/746,147
• Time in Patent Office: 314 Days
• Field of Search: 430/312, 430/313, 430/314, 430/328, 430/330, 430/394
• US Class Current: 430/312
• CPC Class Codes: G03F 7/0035 Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
• CPC Class Codes: G03F 7/40 Treatment after imagewise removal, e.g. baking
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/32139 using masks

Abstract

A new photolithographic process using the method of photoresist double coating to fabricate fine lines with narrow spacing is described. A layer to be etched is provided overlying a semiconductor substrate. The layer to be etched is coated with a first layer of photoresist and baked. The first photoresist layer is exposed to actinic light through openings in a mask and developed to produce the desired first pattern on the surface of the first photoresist wherein the openings have a minimum width of the resolution limit plus two times the misalignment tolerance of the photolithography process. The layer to be etched is coated with a second photoresist layer where the layer to be etched is exposed within the openings in the first photoresist layer. The second photoresist layer is exposed to actinic light through openings in a mask and developed to produce the desired second pattern on the surface of the second photoresist wherein the second pattern alternates with the first photoresist pattern and wherein the spacing between the first and second patterned photoresist coatings has a width equal to the misalignment tolerance. The misalignment tolerance is much smaller than the resolution limit so the line spacing achieved is narrower than the resolution limit of the photolithography process.

Claims

1. A method of forming a double coating photoresist mask to allow line spacing narrower than the photolithography resolution limit in the fabrication of an integrated circuit comprising:

providing a semiconductor substrate including a layer to be etched;

coating said layer to be etched with a first layer of photoresist;

exposing said first photoresist layer to light through a mask, developing said first photoresist layer and removing parts of said first photoresist layer to produce a first pattern from said first photoresist layer having first openings wider than said resolution limit, said first openings flee of photoresist from said first photoresist layer;

hardening said first patterned photoresist layer;

coating said layer to be etched with a second photoresist layer so that said second photoresist layer is within said first openings in said first patterned photoresist layer;

exposing said second photoresist layer to light through a mask, developing said second photoresist layer and removing parts of said second photoresist layer to produce a second pattern from said second photoresist layer having portions of said second pattern within said first openings,

said portions of said second pattern within said first openings having first and second edges on opposing sides of said portion, a first edge separated from said first patterned photoresist layer by a first region of the layer to be etched, and a second edge separated from said first patterned photoresist layer by a second region of the layer to be etched,

said first and second regions of the layer to be etched lying within said first opening; and

wherein at least some of said first and second regions are narrower than said resolution limit of said photolithography process.

2. The method of claim 1, wherein said first patterned photoresist layer is formed on said layer to be etched.

3. The method of claim 2, wherein said second pattern is formed on said layer to be etched.

4. The method of claim 1 wherein said layer to be etched is a stacked gate layer consisting of a polysilicon control gate overlying a dielectric layer overlying a polysilicon floating gate layer.

5. The method of claim 1 wherein said layer to be etched is a metal layer.

6. A method of forming a double coating photoresist mask to allow line widths narrower than the photolithography resolution limit in the fabrication of an integrated circuit comprising:

coating a semiconductor substrate with a first layer of photoresist;

exposing said first photoresist layer to light through a mask, developing said first photoresist layer and removing parts of said first photoresist layer to produce a first patterned photoresist layer having first openings wider than said resolution limit, said first openings free of said first photoresist layer;

hardening said first patterned photoresist layer;

coating said semiconductor substrate with a second photoresist layer so that said second photoresist layer is within said first openings in said first patterned photoresist layer;

exposing said second photoresist layer to light through a mask, developing said second photoresist layer and removing parts of said second photoresist layer to produce a second pattern from said second photoresist layer wherein said second pattern lies within said first openings in said first patterned photoresist layer so that regions of said first patterned photoresist layer are interleaved with regions of said second pattern laterally across at least a portion of said semiconductor substrate, leaving portions of said semiconductor substrate not covered with photoresist between adjacent regions of said first patterned photoresist layer and said second pattern.

7. A method as in claim 6 for forming a double coating resist mask used to form buried bit lines narrower than the photolithography resolution limit, the method further comprising the step of implanting ions into said portions of said semiconductor substrate not covered with photoresist to form said buried bit lines narrower than said resolution limit of said photolithography process.

8. A method as in claim 6, comprising the step of etching said semiconductor substrate not covered by said first and second patterned photoresist layers to form a device having at least some lines narrower than said resolution limit of said photolithography process.

9. A method of forming a double coating photoresist mask to allow for line spacing narrower than the photolithography resolution limit in the fabrication of an integrated circuit comprising:

providing at least one layer to be etched overlying a semiconductor substrate;

coating said layer to be etched with a first layer of photoresist;

exposing said first photoresist layer to light through a mask, developing said first photoresist layer and removing parts of said first photoresist layer to produce a first patterned photoresist layer having first openings wider than said resolution limit as measured along a first direction, said first openings free of photoresist from said first photoresist layer;

hardening said first patterned photoresist layer;

coating said layer to be etched with a second photoresist layer so that said second photoresist layer is within said first openings in said first patterned photoresist layer; and

exposing said second photoresist layer to light through a mask, developing said second photoresist layer and removing parts of said second photoresist layer to produce a second pattern from said second photoresist layer which lies within said first openings in said first patterned photoresist layer so that regions of said first patterned photoresist layer are interleaved with regions of said second pattern laterally along said first direction across at least a portion of said layer to be etched, leaving said layer to be etched not covered with photoresist between adjacent regions of said first patterned photoresist layer and said second pattern.

10. A method as in claim 9 for forming a double coating photoresist mask to allow word line spacing narrower than the photolithography resolution limit in the fabrication of an integrated circuit:

wherein said layer to be etched is formed by providing a gate silicon oxide layer over the surface of said semiconductor substrate and depositing a polysilicon layer over said gate silicon oxide layer; and

etching said polysilicon layer not covered by said first and second patterned photoresist layers to form polysilicon word line spacing narrower than said photolithography resolution limit.

11. A method as in claim 9 wherein said first photoresist layer is baked under ultraviolet light at a temperature of between about 140°

to 160°

C. for between about 50 to 70 seconds.

12. A method as in claim 9 for forming a double coating photoresist mask to allow metal line spacing narrower than the photolithography resolution limit in the fabrication of an integrated circuit:

wherein said layer to be etched is formed by providing an insulating layer overlying said semiconductor substrate and depositing a metal layer overlying said insulating layer;

etching said metal layer not covered by said first and second patterned photoresist layers wherein said metal line spacing achieved is narrower than said resolution limit of said photolithography process.

13. The method of claim 9 wherein said layer to be etched is a polysilicon layer.

14. The method of claim 9 wherein said layer to be etched is a stacked gate layer consisting of a polysilicon control gate overlying a dielectric layer overlying a polysilicon floating gate layer.

15. The method of claim 9 wherein said layer to be etched is a metal layer.

16. The method of claim 9 wherein said first openings have a minimum width of the resolution limit of the photolithography process plus two times the misalignment tolerance of said photolithography process and wherein said second photoresist pattern alternates with said first photoresist pattern and wherein the spacing between said first and second patterned photoresist coatings has a width equal to said misalignment tolerance wherein said misalignment tolerance is smaller than said resolution limit and wherein the line spacing achieved is smaller than said resolution limit of said photolithography process.

17. A method as in claim 9 for forming a double coating photoresist mask to allow line spacing of a stacked gate memory narrower than the photolithography resolution limit in the fabrication of an integrated circuit:

wherein said layer to be etched is formed by providing an insulating layer over the surface of said semiconductor substrate, depositing a polysilicon floating gate layer overlying said insulating layer, depositing an interpoly dielectric layer overlying said polysilicon floating gate layer and depositing a control gate polysilicon layer overlying said interpoly dielectric layer; and

etching said polysilicon control gate layer, said interpoly dielectric layer, and said polysilicon floating gate layer not covered by said first and second patterned photoresist layers to form said stacked gate structures wherein said line spacings achieved are narrower than said photolithography resolution limit.

18. The method of claim 17 wherein said insulating layer is composed of a gate silicon oxide.

19. The method of claim 17 wherein said insulating layer is composed of a tunnel silicon oxide.

20. The method of claim 17 wherein said interpoly dielectric layer is composed of silicon oxide, silicon nitride, and silicon oxide layers.