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Multilayer ceramic chip capacitor

  • US 5,668,694 A
  • Filed: 10/19/1995
  • Issued: 09/16/1997
  • Est. Priority Date: 10/19/1994
  • Status: Expired due to Term
First Claim
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1. A multilayer ceramic chip capacitor having a capacitor chip comprising alternately stacked dielectric layers and internal electrode layers, whereinsaid dielectric layers comprise a dielectric layer material which comprises barium titanate, magnesium oxide, yttrium oxide, at least one selected from barium oxide and calcium oxide, silicon oxide, manganese oxide, and at least one selected from vanadium oxide and molybdenum oxide in such a proportion that there are presentMgO:

  • 0.1 to 3 molY2 O3 ;

    more than 0 to 5 molBaO+CaO;

    2 to 12 molSiO2 ;

    2 to 12 molMnO;

    more than 0 to 0.5 molV2 O5 ;

    0 to 0.3 molMoO3 ;

    0 to 0.3 molV2 O5 +MoO3 ;

    more than 0 molper 100 mol of BaTiO3, provided that the barium titanate, magnesium oxide, yttrium oxide, barium oxide, calcium oxide, silicon oxide, manganese oxide, vanadium oxide, and molybdenum oxide are calculated as BaTiO3, MgO, Y2 O3, BaO, CaO, SiO2, MnO, V2 O5, and MoO3, respectively, and whereinsaid dielectric layer material comprises crystal grains having a mean grain size of up to 0.45 μ

    m, and whereinin an X-ray diffraction chart of said dielectric layer material, a diffraction line of (200) plane and a diffraction line of (002) plane overlap one another to form a wide diffraction line which has a half-value width of up to 0.35°

    .

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