Protection system for critical memory information

• US 5,668,973 A
• Filed: 04/14/1995
• Issued: 09/16/1997
• Est. Priority Date: 04/14/1995
• Status: Expired due to Term

• Current Assignee: Neopost Technologies S.A. (Quadient SA)
• Original Assignee: Ascom Hasler Mailing Systems Incorporated
• Inventors: Muller, Martin, Fluckiger, Daniel, Stutz, Peter
• Primary Examiner(s): Asta, Frank J.
• Application Number:
  US08/422,435
• Time in Patent Office: 886 Days
• Field of Search: 395/479, 395/490, 395/491, 365/189.01
• US Class Current: 711/152
• CPC Class Codes: G07B 17/00193 Constructional details of apparatus in a franking system
• CPC Class Codes: G07B 2017/00258 Electronic hardware aspects, e.g. type of circuits used
• CPC Class Codes: G07B 2017/00403 Memory zones protected from unauthorized reading or writing
• CPC Class Codes: G07B 2017/00967 PSD [Postal Security Device] as defined by the USPS [US Postal Service]

Abstract

A computer system for protecting memory comprising a processor having address outputs and executing a stored program, a memory having a control input, an address-decoder for providing a control signal to the control input of the memory in response to associated address outputs from the processor, and a window circuit. The window circuit comprises a range detector responsive to the address outputs for generating a range-detection signal indicative of an address from the processor being within a protected range, the protected range non-identical to the entirety of the space of addresses within the memory. Access to memory locations within the protected range is permitted only if a request signal is received from the processor. If the request signal is asserted for an unexpectedly long time an error condition is annunciated, for example the processor is reset.

Claims

1. A computer system for protecting memory comprising a processor having address outputs and executing a stored program, a memory having a control input, and window means, said window means comprising:

range detection means responsive to the address outputs for generating a range-detection signal indicative of an address from the processor being within a protected range, the protected range non-identical to the entirety of the space of addresses within the memory;

request means responsive to an output from the processor for recognizing a request from the processor and generating a request signal; and

denying means intermediate the processor and the memory and responsive to the range-detection signal and the request signal for denying the control input to the memory if the range-detection signal is asserted in the absence of the request signal.

2. The computer system of claim 1 wherein the computer system further comprises a postage printer, and wherein the memory contains information indicative of an amount of postage available for printing.

3. The computer system of claim 1 wherein the range detection means further comprises means responsive to receiving a command from the processor indicative of a different range for setting the protected range to the different range.

4. The computer system of claim 3 wherein the request means comprises a first addressable latch, and the command from the processor indicative of a different range comprises a processor write command of a data value to the first addressable latch.

5. The computer system of claim 3 wherein the window means further comprises a second latch means responsive to the command from the processor indicative of the different range for blocking subsequent changes to the protected range.

6. The computer system of claim 5 wherein the request means comprises a first addressable latch, and the command from the processor indicative of a different range comprises a processor write command of a data value to the first addressable latch, and wherein the second latch means comprises a second latch that is reset upon system reset and is set by the processor write command of the data value to the first addressable latch, and wherein the set output of the second latch blocks subsequent writing to the first addressable latch.

7. The computer system of claim 1 further comprising a timing means responsive to the assertion of the request signal and responsive to de-assertion of the request signal, for generating an annunciation output upon the event of the request signal not being de-asserted within a predetermined interval relative to the assertion of the request signal.

8. The computer system of claim 7 wherein the processor further comprises an interrupt input, and wherein the annunciation output of the timer means is operatively coupled to the interrupt input.

9. The computer system of claim 8 further comprising event storage means responsive to receipt of the interrupt signal for storing information indicative of occurrence of the reset signal, the contents of said event storage means available as an input to the processor.

10. The computer system of claim 6 further comprising means permitting the processor to change the predetermined value.

11. The computer system of claim 1 wherein the processor further comprises a write control signal, and wherein the system further comprising means responsive to the denying means for annunciating the event of assertion of the range-detection signal and assertion of the write control signal in the absence of the request signal.

12. A method for protecting memory for use in a computer system comprising a processor having address outputs and executing a stored program, a memory having a control input, and window means, said window means comprising:

range detection means responsive to the address outputs for generating a range-detection signal indicative of an address from the processor being within a protected range, the protected range non-identical to the entirety of the space of addresses within the memory;

request means responsive to an output from the processor for recognizing a request from the processor and generating a request signal; and

denying means intermediate the processor and the memory and responsive to the range-detection signal and the request signal for denying the control input to the memory if the range-detection signal is asserted in the absence of the request signal;

the method comprising the steps of;

receiving address outputs from the processor at the range detection means;

generating the range-detection signal if the address outputs from the processor are indicative of the address from the processor being within the protected range; and

denying the control input to the memory if the range-detection signal is asserted in the absence of assertion of the request signal.

13. The method of claim 12 wherein the window means further comprises a timing means, the method further comprising the steps of:

starting the timing means upon assertion of the request signal;

and

providing an annunciation if the timing means has measured a predetermined interval prior to the request signal no longer being asserted.

14. The method of claim 13 wherein the step of providing the annunciation comprises interrupting the processor.

15. The method of claim 14 wherein the system further comprises event storage means responsive to receipt of the interrupt signal for storing information indicative of occurrence of the interrupt signal, the contents of said event storage means available as an input to the processor, the method further comprising the step, following the interrupting of the processor, of receiving an input from the event storage means.

16. The method of claim 13 wherein the step of providing the annunciation further comprises denying the control input to the memory.

17. The method of claim 12 wherein the denying step further comprises providing an annunciation.

18. The method of claim 17 wherein the step of providing the annunciation comprises interrupting the processor.

19. The method of claim 18 wherein the system further comprises event storage means responsive to receipt of the interrupt signal for storing information indicative of occurrence of the interrupt signal, the contents of said event storage means available as an input to the processor, the method further comprising the step, following the interrupting of the processor, of receiving an input from the event storage means.