Hierarchical fat hypercube architecture for parallel processing systems

• US 5,669,008 A
• Filed: 05/05/1995
• Issued: 09/16/1997
• Est. Priority Date: 05/05/1995
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Lenoski, Daniel E., Galles, Michael B.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/435,451
• Time in Patent Office: 865 Days
• Field of Search: 395/800, 395/311
• US Class Current: 712/12
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes

Abstract

A hierarchical fat hypercube topology provides an infrastructure for implementing a multi-processor system at a plurality of levels. A first level is comprised of a plurality of n-dimensional hypercubes. This plurality of n-dimensional hypercubes is interconnected at a second level utilizing an m-dimensional metacube. The number of dimensions at each level and the number of bristles at each level can be customized depending on the requirements of the application. Additionally, routers can be implemented such that the system can be expanded to meet increasing system requirements. This is particularly useful at the second level of the hierarchical topology.

Claims

1. A hierarchical fat hypercube topology for a multi-processor network, comprising:

a first level comprising a plurality of n-dimensional hypercubes, each said n-dimensional hypercube comprising 2ⁿ first-level nodes; and

a second level comprising a p-dimensional metacube, wherein said metacube comprises 2^p second-level nodes, said one or more second-level nodes each comprising 2 routers for interconnecting said first-level nodes of said first-level n-dimensional hypercubes;

wherein each said n-dimensional hypercube of said first level is connected to a corresponding second-level node of said metacube via 2ⁿ edges;

wherein said 2ⁿ routers are not connected together with edges.

2. The hierarchical fat hypercube topology according to claim 1, wherein said 2ⁿ edges connecting an n-dimensional hypercube of said first level to a corresponding second-level node of said metacube each connect one of said first-level nodes of said n-dimensional hypercube to one of said 2ⁿ routers of said second-level node.

3. The hierarchical fat hypercube topology according to claim 1, wherein said second nodes of said metacube are connected together as a p-dimensional network, wherein specified node pairs are connected together using 2ⁿ edges such that there is one edge for each pair of routers in a specified node pair.

4. The hierarchical fat hypercube topology according to claim 1, wherein there is no more than one n-dimensional hypercube of said first level connected to each second node of said metacube.

5. The hierarchical fat hypercube topology according to claim 1, wherein there are two or more n-dimensional hypercubes of said first level connected to each said node of said metacube.

6. The hierarchical fat hypercube topology according to claim 1, wherein said first-level nodes each comprise a router and one or more hubs, wherein said routers at said first-level nodes comprise ports for connecting to said hubs and for connecting to said routers at other said first-level and said second-level nodes.

7. The hierarchical fat hypercube topology according to claim 6, wherein said hubs comprise one or more processors.

8. The hierarchical fat hypercube topology according to claim 6, wherein said routers at said first-level nodes comprise an identical number of ports as said routers at said second-level nodes.

9. The hierarchical fat hypercube topology according to claim 6, wherein said hubs comprise memory and/or I/O controllers.

10. A hierarchical fat hypercube topology for a multi-processor network, comprising:

a first level comprising a plurality of n-dimensional hypercubes, each said n-dimensional hypercube comprising 2ⁿ first-level nodes, wherein each said first-level node is connected to n other first-level nodes using n first edges;

a second level comprising a p-dimensional metacube, wherein said metacube comprises 2^p second-level nodes, wherein each said second-level node comprises 2ⁿ routers and wherein each said second-level node is connected to p other second-level nodes using p2ⁿ second edges; and

a plurality of third edges for connecting each said n-dimensional hypercube of said first level to one of said second-level nodes, wherein each node of each said n-dimensional hypercube is connected to one of said 2ⁿ routers in one of said second-level nodes;

wherein said 2ⁿ routers are not connected together with edges.

11. The hierarchical fat hypercube topology according to claim 10, wherein there is a no more than one n-dimensional hypercube of said first level connected to each second node of said metacube.

12. The hierarchical fat hypercube topology according to claim 10, wherein there are two n-dimensional hypercubes of said first level connected to each said node of said metacube.

13. The hierarchical fat hypercube topology according to claim 10, wherein said first-level nodes each comprise a router and one or more hubs, wherein said routers at said first-level nodes comprise ports for connecting to said hubs and for connecting to said routers at other said first-level and said second-level nodes.

14. The hierarchical fat hypercube topology according to claim 13, wherein said hubs comprise one or more processors.

15. The hierarchical fat hypercube topology according to claim 13, wherein said routers at said first-level nodes comprise an identical number of ports as said routers at said second-level nodes.

16. The hierarchical fat hypercube topology according to claim 13, wherein said hubs comprise memory and/or I/O controllers.