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Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units

  • US 5,669,010 A
  • Filed: 03/06/1996
  • Issued: 09/16/1997
  • Est. Priority Date: 05/18/1992
  • Status: Expired due to Term
First Claim
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1. A Single Instruction Multiple Data (SIMD) two-stage computational machine comprising:

  • a top computational stage directly cascaded to a bottom computational stage without any intermediate intervening computational stage;

    said top computational stage including;

    top multi-port memory means for storing data having a plurality of inputs and a plurality of outputs; and

    at least one top arithmetic unit for processing said data coupled to at least one of the top memory means outputs, and each one of said top arithmetic units having an output coupled to at least one of the top memory means inputs;

    said bottom computational stage including;

    bottom multi-port memory means for storing data having a plurality of inputs and a plurality of outputs, the bottom memory means inputs being directly coupled to the top arithmetic unit outputs without any intervening processor stages; and

    at least one bottom arithmetic unit for processing said data coupled to at least one of the bottom memory means outputs, and each one of said bottom arithmetic units having an output coupled to at least one of the bottom memory means inputs; and

    an instruction bus coupled to said top memory means, to said top arithmetic units, to said bottom memory means, and to said bottom arithmetic units, for simultaneously specifying the same single instruction to each stage of said two-stage computational machine, said single instruction simultaneously specifying a plurality of operations including all the operations of each of said top and bottom arithmetic units, and all memory means address and control operations; and

    a plurality of busses for providing simultaneous plural input and output operations, said plurality of busses including;

    an input bus for coupling operands from a first external operand source to said top memory means;

    an output bus for coupling arithmetic unit results stored in said bottom memory means to an external destination for said results; and

    at least one auxiliary data input means for optionally coupling special operands from a second external operand source to one of said top or bottom arithmetic units.

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