Vertical insulated gate semiconductor device having high current density and high reliability

  • US 5,670,811 A
  • Filed: 04/28/1995
  • Issued: 09/23/1997
  • Est. Priority Date: 08/24/1987
  • Status: Expired due to Term
First Claim
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1. An insulated gate semiconductor device, comprising:

  • (a) a semiconductor substrate having a pair of main surfaces;

    a first semiconductor region of a first conductivity type, forming one of the pair of main surfacesa second semiconductor region of a second conductivity type adjacent to said first semiconductor region and forming the other of the pair of main surfaces,a plurality of third semiconductor regions of the first conductivity type extending from the other of the pair of main surfaces into said second semiconductor region, such that a respective portion of the second semiconductor region is exposed between two adjacent third semiconductor regions, andtwo fourth semiconductor regions, of the second conductivity type, extending from the other of the pair of main surfaces into each of said third semiconductor regions, each of the fourth semiconductor regions having opposed sides;

    (b) a first main electrode connected to said first semiconductor region at the one of the pair of main surfaces of the semiconductor substrate;

    (c) a second main electrode connected to said third semiconductor regions and said fourth semiconductor regions at the other of the pair of main surfaces of the semiconductor substrate; and

    (d) a plurality of insulating gates formed on the other of the pair of main surfaces, each of said plurality of insulating gates being formed (1) on a respective exposed portion of the second semiconductor region, (2) on portions of two adjacent third semiconductor regions having the respective exposed portion of the second semiconductor region therebetween, and (3) on fourth semiconductor regions, in said two adjacent third semiconductor regions, having only said portions of the two adjacent third semiconductor regions and said respective exposed portion of the second semiconductor region therebetween, and each of said insulating gates having a gate oxide film on the other of the pair of main surfaces of the semiconductor substrate, a gate electrode formed on said gate oxide film, and an insulating film formed on said gate electrode, each of said plurality of third semiconductor regions being aligned with two sides of two insulating gates adjacent to a respective third semiconductor region, wherein both of the opposed sides of each of said fourth semiconductor regions are aligned only to a respective side of said insulating gate adjacent to the respective fourth semiconductor region, and wherein a length of each of said insulating gates, from one side to another opposed side of each insulating gate, is longer than a distance between adjacent sides of adjacent insulating gates.

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