Low drop-out voltage regulator having high ripple rejection and low power consumption

• US 5,672,959 A
• Filed: 04/12/1996
• Issued: 09/30/1997
• Est. Priority Date: 04/12/1996
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Micro Linear Corporation (Qorvo, Inc.)
• Inventors: Der, Lawrence
• Primary Examiner(s): KRISHNAN, ADITYA
• Application Number:
  US08/631,403
• Time in Patent Office: 536 Days
• Field of Search: 323/273, 323/265, 323/267, 323/268, 323/272, 323/224, 323/222, 323/289, 323/282, 363/71
• US Class Current: 323/273
• CPC Class Codes: G05F 3/247 producing a voltage or current as a predetermined function of the supply voltage

Abstract

A low drop-out regulator circuit that has high ripple rejection and low power consumption. A first local feedback loop is a high-speed, high-bandwidth loop that actively rejects noise from the input source to the regulator. A second feedback loop, having lower speed and a correspondingly lower bandwidth than the first feedback loop, regulates the output voltage. Each feedback loop is separately optimized for its respective bandwidth requirements and, therefore, the regulator is highly efficient. The first feedback loop comprises an amplifier and a pair of PMOS transistors configured as a current mirror with current gain. The first feedback loop generates a first current for charging an output capacitor. Feedback ensures that the first current is proportional to a second current generated by the second feedback loop while rejecting noise from the input source. The second feedback loop comprises a transconductance amplifier that controls the second current with feedback such that the first current charges the output capacitor to the desired output voltage level. The second loop has a lower bandwidth than the first loop because the bandwidth of the second feedback loop is dominated by a relatively large output capacitance and compensation capacitance, while the bandwidth of the first feedback loop is dominated by the relatively small gate capacitances of the pair of transistors and a relatively small compensation capacitance.

Claims

1. A voltage regulator comprising:

a. a first feedback loop for attenuating noise from a power source having a first bandwidth; and

b. a second feedback loop including a capacitor and having a second bandwidth is coupled to the first feedback loop for generating an output voltage across the capacitor wherein the second bandwidth is limited by a capacitance of the capacitor and the first bandwidth is independent of the capacitance.

2. The voltage regulator according to claim 1 wherein the first bandwidth is greater than the second bandwidth.

3. The voltage regulator according to claim 1 wherein the first feedback loop comprises an active current mirror wherein the active current mirror has an output resistance that is greater than an on-resistance of a transistor.

4. A voltage regulator comprising:

a. a current mirror for forming a first current wherein the first current is proportional to a second current;

b. a capacitor coupled to receive the first current for forming an output voltage; and

c. a transconductor coupled to generate the second current based upon a comparison of the output voltage to a reference voltage.

5. The voltage regulator according to claim 4 wherein the current mirror has an output resistance that is greater than an on-resistance of a transistor.

6. The voltage regulator according to claim 4 wherein the current mirror comprises a first feedback loop, the first feedback loop for maintaining the first current proportional to the second current and wherein the transconductor comprises a second feedback loop, the second feedback loop for maintaining the output voltage at a predetermined level.

7. The voltage regulator according to claim 6 wherein the first feedback loop comprises two loops including a negative feedback loop and a positive feedback loop.

8. The voltage regulator according to claim 6 wherein the first feedback loop has a first bandwidth and the second circuit has a second bandwidth and further wherein the first bandwidth is higher than the second bandwidth.

9. The voltage regulator according to claim 6 wherein the first feedback loop has a first response time for controlling the first current and the second feedback loop has a second response time for controlling the second current wherein first response time is shorter than the second response time.

10. A voltage regulator comprising:

a. a first circuit for forming a first current wherein the first current is proportional to a second current; and

b. a second circuit for generating the second current coupled to receive the first current wherein the second circuit controls the second current such that the first current charges a storage element to a predetermined voltage level for powering a load.

11. The voltage regulator according to claim 10 wherein the first circuit comprises a current mirror.

12. The voltage regulator according to claim 11 wherein the current mirror has an output resistance that is greater than an on-resistance of a transistor.

13. The voltage regulator according to claim 11 wherein the current mirror is coupled to receive power from a power source wherein the power source comprises a switching regulator.

14. The voltage regulator according to claim 10 wherein the second circuit comprises a transconductance amplifier coupled to generate the second current based upon a comparison of a voltage representative of an output voltage to a reference voltage.

15. The voltage regulator according to claim 10 wherein the first circuit comprises a first feedback loop for maintaining the first current proportional to the second current and wherein the second circuit comprises a second feedback loop for maintaining the output voltage at the predetermined level.

16. The voltage regulator according to claim 15 wherein the first feedback loop has a first bandwidth and the second circuit has a second bandwidth and further wherein the first bandwidth is higher than the second bandwidth.

17. The voltage regulator according to claim 15 wherein the first feedback loop has a first response time for controlling the first current and the second feedback loop has a second response time for controlling the second current wherein first response time is shorter than the second response time.

18. A method of regulating a voltage comprising the steps of:

a. forming a first current according to a difference between a voltage representative of an output voltage and a reference voltage;

b. forming a second current wherein the second current is proportional to the first current; and

c. charging a capacitor with the second current for forming the output voltage.

19. The method according to claim 18 wherein a response time for the step of forming the second current is shorter than a response time for the step of forming the first current.

20. The method according to claim 19 wherein the response time for the step of forming the first current is dependent upon a capacitance of the capacitor and the response time for the step of forming the second current is independent of the capacitance.

21. A voltage regulator comprising:

a. a first transistor having a first source, a first drain and a first gate;

b. a second transistor having a second source, a second drain and a second gate, wherein the first source is coupled to the second source;

c. an amplifier having a first amplifier input, a second amplifier input and an amplifier output, wherein the first drain is coupled to the first amplifier input, the second drain is coupled to the second amplifier input and the amplifier output is coupled to the first gate and to the second gate;

d. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor is coupled to the second drain;

e. a transconductance amplifier having a first transconductance input, a second transconductance input and a transconductance output wherein the first transconductance input is coupled to the second terminal of the first resistor, the second transconductance input is coupled to receive a reference voltage level and the transconductance output is coupled to the first drain;

f. a second resistor having a first terminal and a second terminal wherein the first terminal of the second resistor is coupled to the second terminal of the first resistor and the second terminal of the second resistor is coupled to a ground node; and

g. a capacitor having a first terminal and a second terminal wherein the first terminal of the capacitor is coupled to the second drain and the second terminal of the capacitor is coupled to the ground node.

22. The regulator according to claim 21 further comprising a load coupled across the capacitor.

23. The regulator according to claim 21 further comprising a third resistor having a first terminal and second terminal wherein a first terminal of the third resistor is coupled to the first amplifier input and the second terminal of the third resistor is coupled to the second amplifier input.

24. The regulator according to claim 21 wherein the first transistor has an aspect ratio that is smaller than an aspect ratio of the second transistor.