Process of fabricating a self-aligned thin-film transistor for a liquid crystal display

• US 5,674,757 A
• Filed: 05/30/1995
• Issued: 10/07/1997
• Est. Priority Date: 05/28/1994
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Kyu
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US08/454,027
• Time in Patent Office: 861 Days
• Field of Search: 437/21, 437/40 TFI, 437/41 TFI, 437/101, 437/187, 437/909, 437/229
• US Class Current: 438/159
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A self-aligned thin-film transistor, fabricated by depositing a conductive layer on a transparent insulating substrate, etching the conductive layer so as to form a gate electrode together with gate lines, forming a triple layer having of a gate insulating layer, a semiconductor layer and an extrinsic semiconductor layer sequentially deposited over the substrate, etching the triple layer so that only a part thereof covering the gate electrode only remains to form an active pattern, depositing a transparent conductive layer over the substrate to form a drain electrode part by etching the transparent conductive layer so that a part of the transparent conductive layer remains overlapping the gate electrode, depositing a negative photoresist over the substrate, exposing the negative photoresist to a light supplied from the back of the transparent substrate opposite the gate and developing the thus-exposed photoresist, forming a drain electrode by removing the part of a transparent conductive layer appearing in a region over the gate wherefrom the photoresist is removed, depositing a conductive layer over the substrate to form a source electrode together with data lines by etching the conductive layer so that there remains a portion of the conductive layer opposite to the drain electrode with respect to the gate electrode, and removing a portion of the extrinsic semiconductor layer exposed over the gate electrode so as to form a channel.

Claims

1. A process for fabricating a self-aligned thin-film transistor comprising the steps of:

depositing a conductive layer on a transparent insulating substrate;

etching said conductive layer so as to form a gate electrode together with gate lines;

forming a triple layer consisting of a gate insulating layer, a semiconductor layer and an extrinsic semiconductor layer sequentially deposited over said substrate;

etching said triple layer so that only a part thereof covering said gate electrode remains to form an active pattern;

depositing a transparent conductive layer over said substrate to form a drain electrode part by etching said transparent conductive layer so that a part of said transparent conductive layer remains overlapping said gate electrode;

depositing a negative photoresist over said substrate;

exposing said negative photoresist to a light supplied from the back of said transparent substrate opposite said gate and developing the thus-exposed negative photoresist;

forming a drain electrode by removing a part of said transparent conductive layer appearing in a region over said gate from which said photoresist is removed;

depositing a conductive layer over said substrate to form a source electrode together with data lines, by etching said conductive layer so that there remains a portion of said conductive layer opposite to said drain electrode with respect to said gate electrode; and

removing a portion of said extrinsic semiconductor layer exposed over said gate electrode so as to form a channel.

2. A process for fabricating a self-aligned thin-film transistor as defined in claim 1, wherein the conductive layer used for forming said gate electrode and gate lines is aluminum.

3. A process for fabricating a self-aligned thin-film transistor as defined in claim 2, further comprising the step of subjecting said gate electrode to anodic oxidation.

4. A process for fabricating a self-aligned thin-film transistor as defined in claim 1, wherein the amount of said drain electrode overlapping said gate electrode is determined by controlling the duration of exposure of said negetive photoresist to said light.

5. A process for fabricating a self-aligned thin-film transistor as defined in claim 1, wherein said conductive layer used for forming said source electrode is a transparent material.

6. A process for fabricating a self-aligned thin-film transistor as defined in claim 5, wherein the step of forming said source electrode further comprises the steps of:

depositing a transparent conductive material over said substrate to form a source electrode part by etching said transparent conductive layer so that a part of said transparent conductive layer remains overlapping said gate electrode;

depositing a negative photoresist over said substrate;

exposing said negative photoresist to a light supplied from the back of said transparent substrate opposite said gate and developing said negative photoresist; and

forming a source electrode by removing the part of said transparent conductive layer appearing in a region over said gate from which said photoresist is removed.

7. A process for fabricating a self-aligned thin-film transistor as defined in claim 6, wherein the amount of said source electrode overlapping said gate electrode is determined by controlling the duration of exposure of said negetive photoresist to said light.

8. A process for fabricating a self-aligned thin-film transistor comprising the steps of:

depositing a conductive layer on a transparent insulating substrate;

etching said conductive layer so as to form a gate electrode together with gate lines;

forming a triple layer consisting of a gate-insulating layer, a semiconductor layer and an extrinsic semiconductor layer sequentially deposited over said substrate;

etching said triple layer so that only a part thereof covering said gate electrode only remains to form an active pattern;

depositing a transparent conductive layer over said substrate to form a drain and source electrode parts by etching said transparent conductive layer so that two parts of said transparent conductive layer remain facing each other with a space between them and overlapping said gate electrode;

depositing a negative photoresist over said substrate;

exposing said negative photoresist to a light supplied from the back of said transparent substrate opposite said gate and developing the thus-exposed negative photoresist;

forming a drain and source electrodes by removing the parts of said transparent conductive layer appearing in a region over said gate from which said photoresist is removed; and

removing a portion of said extrinsic semiconductor layer exposed over said gate electrode so as to form a channel.

9. A process for fabricating a self-aligned thin-film transistor as defined in claim 8, wherein the amount of said source and drain electrodes overlapping said gate electrode is determined by controlling the duration of exposure of said negetive photoresist to said light.

10. A process for fabricating a self-aligned thin-film transistor comprising the steps of:

depositing a conductive layer on a transparent insulating substrate;

etching said conductive layer so as to form a gate electrode together with gate lines;

forming a triple layer consisting of a gate insulating layer, a semiconductor layer and an extrinsic semiconductor layer sequentially deposited over said substrate;

etching said triple layer so that only a part thereof covering said gate electrode only remains to form an active pattern;

etching the gate insulating layer of a connecting pad for connecting a drive integrated circuit with a liquid crystal substrate;

depositing a transparent conductive layer over said substrate to form a drain electrode part by etching said transparent conductive layer so that a part of said transparent conductive layer remains overlapping said gate electrode and a part of said transparent conductive layer over said connecting pad is not etched;

depositing a negative photoresist over said substrate;

exposing said negative photoresist to a light supplied from the back of said transparent substrate opposite said gate and developing the thus-exposed negative photoresist;

forming a drain electrode by removing the part of said transparent conductive layer appearing in a region over said gate from which said photoresist is removed;

depositing a conductive layer over said substrate to form a source electrode together with data lines by etching said conductive layer so that there remains a portion of said conductive layer opposite to said drain electrode with respect to said gate electrode; and

removing a portion of said extrinsic semiconductor layer exposed over said gate electrode so as to form a channel.