Memory cell array for digital spatial light modulator

• US 5,682,174 A
• Filed: 02/16/1995
• Issued: 10/28/1997
• Est. Priority Date: 02/16/1995
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chiu, Edison H.
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): LAO, LUNYI
• Application Number:
  US08/389,674
• Time in Patent Office: 985 Days
• Field of Search: 345/84, 345/85, 345/86, 345/212, 345/211, 345/213, 345/87, 345/94, 345/95, 345/55, 345/98, 348/770, 348/771, 365/154, 349/1, 349/33, 349/34
• US Class Current: 345/84
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

A spatial light modulator (SLM) (20) having a pixel array (21) and a memory cell array (21a). Drivers (23c, 24b, 26, 27, 28) for the memory cell inputs permit pixels (10) of the SLM (20) to be addressed at a higher voltage than the voltage used for peripheral control circuitry (22, 23, 24). Each driver (23c, 24b, 26, 27, 28) has appropriate logic for providing an input signal to the memory cell array (21a) and a voltage translator (60) for changing the voltage level of that signal.

Claims

1. A spatial light modulator, comprising:

(a) an array of electrically addressable pixels;

(b) an array of memory cells arranged in rows and columns, each said memory cell being in electrical communication with at least one of said pixels; and

(c) control circuitry controlling said array of memory cells, including;

(i) a bit-line associated with each said column of said memory cells, each said bit-line for delivery pixel data to at least one said memory cell;

(ii) a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling said row of said memory cells to be written with said pixel data; and

(d) a bit-line driver circuit increasing a voltage level of said pixel data before said pixel data is delivered to said memory cells, said bit-line driver circuit operating on a first power supply and said control circuitry operating on a second power supply independent from said first power supply.

2. The spatial light modulator of claim 1, wherein there is a one-to-one correspondence between said memory cells and said pixels.

3. The spatial light modulator of claim 1, wherein said write word-line driver circuit has logic circuitry combining an enable signal with said pixel data and has a voltage translator in series connection with said logic circuitry.

4. The spatial light modulator of claim 1, wherein each said memory cell has a first latch feeding a second latch, said first latch transferring said pixel data to said second latch as a function of a transfer signal provided on a transfer line, said transfer line having a transfer signal driver circuit increasing a voltage of said transfer signal.

5. The spatial light modulator of claim 1, further comprising a read word-line associated with each said row of said memory cells, each said read word-line delivering a read signal enabling said pixel data to be read from said memory cell.

6. The spatial light modulator of claim 1, wherein each said pixel comprises a deflectable mirror fabricated over a pair of address electrodes, said address electrodes being connected to said associated memory cell.

7. The spatial light modulator of claim 1, further comprising a write word-line driver circuit increasing a voltage level of said write signal before delivered to said memory cells.

8. The spatial light modulator of claim 7, wherein each write word-line is associated with a single row of said pixels.

9. The spatial light modulator of claim 7, wherein said write word-line driver circuit has logic circuitry for combining said write signal with an address signal and a voltage translator in series connection with said logic circuitry.

10. A spatial light modulator, comprising:

(a) an array of electrically, addressable pixels;

(b) an array of memory cells arranged in rows and columns, each said memory cell being in electrical communication with at least one of said pixels; and

(c) control circuitry controlling said array of memory cells, including;

(i) a bit-line associated with each said column of said memory cells, each said bit-line for delivery pixel data to at least one said memory cell;

(ii) a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling said row of said memory cells to be written with said pixel data; and

(d) a bit-line driver circuit increasing a voltage level of said pixel data before said pixel data is delivered to said memory cells, wherein a single said memory cell stores said pixel data for multiple said pixels.

11. A spatial light modulator, comprising:

(a) an array of electrically addressable pixels;

(b) an array of memory cells arranged in rows and columns, each said memory cell being in electrical communication with at least one of said pixels; and

(c) control circuitry controlling said array of memory cells, including;

(i) a bit-line associated with each said column of said memory cells, each said bit-line for delivery pixel data to at least one said memory cell;

(ii) a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling said row of said memory cells to be written with said pixel data; and

(d) a bit-line driver circuit increasing a voltage level of said pixel data before said pixel data is delivered to said memory cells, wherein each word-line is associated with multiple said rows of said pixels.

12. A digital micromirror device, comprising:

a mirror element array, each said mirror element being addressable via at least one address electrode and tilting in response to an address signal applied at said address electrode;

a memory cell array arranged in columns and rows storing data representing a state of said address signal, each said memory cell being in electrical communication with at least one of said mirror elements via at least one said address electrode, each said memory cell having a first latch that transfers said data to a second latch in response to a transfer signal, said second latch providing said electrical communication of said address signal, to said address electrode;

a bit-line associated with each said column of said memory cell array, each said bit-line delivering said data down one said column of said memory cells to at least one said memory cell, each said bit-line having a bit-line driver circuit changing a voltage level of said data before said data is delivered to said memory cell;

a write word-line associated with each said row of said memory cells, each said write word-line delivering a write signal enabling one said row of said memory cells to be written with said data, each said write word-line having a word-line driver circuit changing a voltage level of said write signal; and

a transfer signal driver circuit changing a voltage level of said transfer signal.

13. The device of claim 12, further comprising a data loading circuit receiving said data on a row-by-row basis, and delivering said row data to said memory cells via said bit-lines.

14. The device of claim 13, further comprising a row selector determining which said row of said memory cells receives said row of data.

15. The device of claim 12, wherein each said pixel has a true said address electrode and a complement said address electrode, and wherein said second latch has a true output and a complement output connected to one said address electrode.