Technique for producing small islands of silicon on insulator

• US 5,691,230 A
• Filed: 09/04/1996
• Issued: 11/25/1997
• Est. Priority Date: 09/04/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/706,230
• Time in Patent Office: 447 Days
• Field of Search: 437/61, 437/62, 437/67, 437/72, 437/73, 148/DIG. 50
• US Class Current: 438/412
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76208 using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Claims

1. A method for manufacturing a silicon on insulator substrate, comprising the steps of:

directionally etching a silicon substrate, to form a plurality of trenches between protruding silicon rows;

forming a silicon nitride cap on the silicon rows, extending partway down the sides of the trenches;

isotropically etching the trenches, to partially undercut the silicon rows; and

oxidizing the substrate, to fully undercut the silicon rows.

2. The method of claim 1, wherein the silicon substrate has a {100} crystallographic orientation and the directional etch is in the <

100>

direction.

3. The method of claim 1, wherein the directional etchant comprises a reactive ion etch.

4. The method of claim 1, wherein the isotropic etchant comprises hydrofluoric acid.

5. The method of claim 1, wherein the silicon rows have a width dimension of one micron or less.

6. The method of claim 1, wherein the silicon rows have a width dimension of 0.25 microns or less.

7. The method of claim 1, wherein the directional etch is approximately as deep as the width of the silicon rows and approximately as wide as the width of the silicon rows.

8. The method of claim 1, wherein the oxidizing step comprises oxidizing the substrate in a wet oxidizing ambient at a temperature of approximately 900 to 1,100 degrees Celsius.

9. The method of claim 1, and further comprising the step of:

defining a plurality of active areas on the silicon rows by local oxidation of silicon.

10. The method of claim 9, and further comprising the step of:

forming a transistor on each of a plurality of the active areas.