Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor

• US 5,696,913 A
• Filed: 06/07/1995
• Issued: 12/09/1997
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Balmer, Keith, Gove, Robert J., Guttag, Karl Marion, Ing-Simmons, Nicholas Kerin
• Primary Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/472,827
• Time in Patent Office: 916 Days
• Field of Search: 395/311, 395/200.08, 395/477, 395/312
• US Class Current: 710/317
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. Each processor has a register with a plurality of read only bits which uniquely identify that processor within the multi-processing system. The processor may employ this unique processor identifier to compute the base address corresponding to that processor. This enables programs which may execute independently of the processor within the multi-processing system.

Claims

1. A multi-processing system comprising:

a plurality of m memories, each of said m memories having a unique addressable memory portion of a single memory address space;

a plurality of n processors, where n is less than m and each of said n processors has a predetermined plurality of corresponding memories, said predetermined plurality of memories corresponding to each processor having a corresponding base address within said single memory address space, each of said processors generating addresses for read/write access to data stored within said plurality of m memories in accordance with received instructions, and each of said processors having an identification register with a plurality of read only bits having stored therein a unique identifier to said processor;

a switch matrix connected to said plurality of m memories and said plurality of n processors responsive to an address generated by said processors to selectively route data between a one of said plurality of n processors and a one of said plurality of m memories whose unique addressable memory portion encompasses said address.

2. The multi-processing system of claim 1, wherein:

said plurality of read only bits of said identification register of each of said plurality of n processors stores a unique processor number in a set of consecutive processor numbers.

3. The multi-processing system of claim 1, wherein:

said identification register of each of said plurality of n processors includes at least one read/write bit.

4. The multi-processing system of claim 1, wherein:

each of said plurality of n processors includes an address unit including

a set of base address registers,

a set of index address registers,

a full adder having a first input connected to said set of base address registers and a second input connected to said set of index address registers, a control input selecting addition or subtraction, and an output, and

an instruction decode circuit connected to said set of base address registers, said set of index registers and said full adder selecting a particular one of said set of base address registers for supply to said first input of said full adder, selecting a particular one of said set of index address registers for supply to said second input of said full adder, and selecting addition or subtraction by said full adder, said output of said full adder being the address generated.

5. The multi-processing system of claim 1, wherein:

each of said plurality of n processors includes

an address generator generating an address corresponding to one of said plurality of addressable memory storage locations of said single memory address space, said address generator including a plurality of address registers, and

a bus connected to said identification register and said plurality of address registers of said address generator for moving data from said identification register to an instruction specified one of said plurality of address registers in response to a register move instruction specifying said identification register as a source and one of said plurality of address registers as said destination.

6. The multi-processing system of claim 1, wherein:

each of said plurality of n processors includes

a plurality of data registers for storing data, and

a bus connected to said identification register and said plurality of data registers for moving data from said identification register to an instruction specified one of said plurality of data registers in response to a register move instruction specifying said identification register as a source and one of said plurality of data registers as said destination.

7. The multi-processing system of claim 1, wherein:

each of said plurality of n processors includes

an address generator generating an address corresponding to one of said plurality of addressable memory storage locations of said single memory address space, and

a data bus connected to said identification register and said data port of said data memory for moving data from said identification register to one of said plurality of addressable memory storage locations of said memory corresponding to said address generated by said address generator in response to a register store instruction specifying said identification register as said destination.

8. In a multi-processing system having a plurality of m memories, each of said m memories having a unique addressable memory portion of a single memory address space, and a plurality of n processors, where n is less than m and each of said n processors has a predetermined plurality of corresponding memories, said predetermined plurality of memories corresponding to each processor having a corresponding base address within said single memory address space, each of said processors generating addresses for read/write access to data stored within said plurality of m memories in accordance with received instructions, the method of addressing memory comprising the steps of:

reading at a particular one of said plurality of n processors an identification register having stored therein a unique identifier to said particular processor; and

calculating an address within said single memory address space corresponding to said particular processor bases upon said unique identifier to said particular processor.

9. The method of addressing memory of claim 8, further comprising:

storing said unique identifier to said particular processor in a plurality of read only bits within said identification register upon manufacture of said multi-processing system.

10. The method of addressing memory of claim 9, wherein:

said step of storing said unique identifier to said particular processor in a plurality of read only bits consists of storing a unique processor number in a set of consecutive processor numbers.

11. The method of addressing memory of claim 8, further comprising:

providing an identification register corresponding to each of said plurality of n processors having said unique identifier to said corresponding processor stored therein; and

said step of reading at a particular one of said plurality of n processors an identification register having stored therein a unique identifier to said particular processor consists of reading said corresponding identification register.