Memory paging system and method including compressed page mapping hierarchy

• US 5,696,927 A
• Filed: 12/21/1995
• Issued: 12/09/1997
• Est. Priority Date: 12/21/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cox, Steve, MacDonald, James R., Dutton, Drew
• Primary Examiner(s): Kim, Matthew M.
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US08/576,100
• Time in Patent Office: 719 Days
• Field of Search: 395/413, 395/888, 395/415, 395/417, 395/403, 395/412, 395/416, 395/418, 395/419, 395/460-463, 395/455, 395/497.01-497.04
• US Class Current: 711/207
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/401 Compressed data

Abstract

A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.

Claims

1. A memory paging system for a computer having a memory and an execution unit addressing the memory using virtual addresses, the memory paging system comprising:

an address mapping hierarchy, the address mapping hierarchy including a plurality of page tables having page table entries mapping from a first portion of virtual addresses to respective pages in physical memory;

a compressed page mapping hierarchy, the compressed page mapping hierarchy including a plurality of compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory;

a translation lookaside buffer for caching recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory; and

a compression/decompression component including a compression/decompression engine coupled between the memory and the execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer.

2. A memory paging system, as recited in claim 1, wherein the address mapping hierarchy and the compressed page mapping hierarchy are represented in the memory, and wherein the compression/decompression component further includes:

a decompression fault handler executable on the execution unit; and

a compression fault handler executable on the execution unit;

wherein decompression fault handler and compression fault handler respectively trigger decompression and compression operations of the compression/decompression engine;

decompression fault handler and compression fault handler updating the states of address mapping hierarchy and compressed page mapping hierarchy in correspondence with transformations between uncompressed and compressed representations of a given page.

3. A memory paging system, as recited in claim 1, wherein the translation lookaside buffer is organized as fully associative cache with a least recently used replacement policy.

4. A memory paging system, as recited in claim 2, wherein the decompression fault handler is responsive to a faulting memory access and comprises:

means for allocating a new memory page;

means for supplying a physical address of the new memory page to the compression/decompression engine;

means for supplying a virtual address of the faulting memory access to the compression/decompression engine;

means for triggering decompression by the compression/decompression engine, the decompression being from a compressed representation of the page corresponding to the faulting memory access to an uncompressed representation of same at the new memory page; and

means for updating the address mapping hierarchy to indicate the physical address of the new memory page and uncompressed state of the corresponding page.

5. A memory paging system, as recited in claim 4, wherein the decompression fault handler communicates with the compression/decompression engine via control registers.

6. A memory paging system, as recited in claim 4, wherein the decompression fault handler communicates with the compression/decompression engine via a stack.

7. A memory paging system, as recited in claim 2, wherein the compression fault handler is responsive to a spill from the translation lookaside buffer and comprises:

means for scanning a free-list for a new block in a compressed memory space;

means for supplying a physical address of the new block to the compression/decompression engine;

means for supplying a virtual address of the faulting memory access to the compression/decompression engine;

means for triggering compression by the compression/decompression engine, the compression being from an uncompressed representation of the page corresponding to the faulting memory access to an compressed representation of same at the new block;

means for updating the address mapping hierarchy to indicate the compressed state of the corresponding page; and

means for updating the compressed page mapping hierarchy to indicate the physical address and size of the corresponding compressed page.

8. A memory paging system, as recited in claim 7, wherein the compression fault handler communicates with the compression/decompression engine via control registers.

9. A memory paging system, as recited in claim 7, wherein the compression fault handler communicates with the compression/decompression engine via a stack.

10. A memory paging system, as recited in claim 1, wherein the compression/decompression component is integrated with an address translation component of an operating system.

11. A memory paging system, as recited in claim 2, wherein the page table entries of the address mapping hierarchy include a compressed page indication for indicating the compression state of the respective page, and wherein compression/decompression component triggers decompression fault handler in response to a compressed page indication.

12. In a memory paging system for a computer having an execution unit, a memory including a hierarchy of data stores for encoding a mapping from virtual memory addresses to physical memory addresses, and a translation lookaside buffer for caching recently-used virtual to physical address mappings, a compression/decompression subsystem comprising:

a compression/decompression engine coupled between the execution unit and the memory for alternately compressing and expanding memory-resident pages;

means residing in the hierarchy of data stores for identifying a compression state of memory-resident pages, the compression state identifying means triggering a compression fault upon a spill from the translation lookaside buffer, the compression state identifying means triggering a decompression fault upon an access to a memory page not represented in the translation lookaside buffer and identified as compressed by the compression state identifying means;

a decompression fault handler responsive to the decompression fault, the decompression fault handler allocating memory for a decompressed memory page, triggering a decompression operation of the compression/decompression engine, and updating the hierarchy of data stores in accordance with the decompression operation; and

a compression fault handler responsive to the compression fault, the compression fault handler scanning a free-list for a target memory block, triggering compression operation of the compression/decompression engine, and updating the hierarchy of data stores in accordance with the compression operation.

13. A compression/decompression subsystem, as recited in claim 12 wherein the means residing in the hierarchy of data stores for identifying a compression state of memory-resident pages includes a compressed page indicating field in page table entries corresponding to memory resident pages.

14. A compression/decompression subsystem, as recited in claim 12 further comprising:

means residing in the hierarchy of data stores for identifying a compressed representation of the page corresponding to a given virtual memory address.

15. A compression/decompression subsystem, as recited in claim 14, wherein the means residing in the hierarchy of data stores for identifying a compressed representation of the page corresponding to a given virtual memory address includes compressed page table entries, each compressed page table entry having a compressed page base address field and a compressed page size field, the compressed page base address and compressed page size fields identifying a variable-size block in the memory containing the compressed representation of the page corresponding to the given virtual memory address.

16. In a memory paging and compression system, a method for handling a decompression fault arising from a faulting memory access, the method comprising the steps of:

allocating a new memory page;

supplying a physical address of the new memory page to a compression/decompression engine;

supplying a virtual address of the faulting memory access to the compression/decompression engine;

triggering decompression by the compression/decompression engine, the decompression being from a compressed representation of the page corresponding to the faulting memory access to an uncompressed representation of same at the new memory page; and

updating an address mapping hierarchy to indicate the physical address of the new memory page and uncompressed state of the corresponding page.

17. A method for handling a decompression fault, as recited in claim 16, comprising the additional steps of:

mapping to the compressed representation in memory using the virtual address of the faulting memory access supplied in the virtual address supplying step, a portion of the virtual address indexing into a corresponding compressed page table entry, wherein the compressed page table entry includes compressed page base address and compressed page size fields identifying a variable-size block in memory containing the compressed representation of the page corresponding to the virtual address; and

decompression the variable-sized block identified in the compressed representation mapping step into the new memory page.

18. A method for handling a decompression fault, as recited in claim 16, wherein the physical address supplying step and the virtual address supplying step include pushing the physical address and the virtual address to a stack.

19. In a memory paging and compression system, a method for handling a compression fault, the method comprising the steps of:

scanning a free-list for a new block in a compressed memory space;

supplying a physical address of the new block to a compression/decompression engine;

supplying a virtual address of a faulting memory access to the compression/decompression engine;

triggering compression by the compression/decompression engine, the compression being from an uncompressed representation of the page corresponding to the faulting memory access to an compressed representation of same at the new block;

updating an address mapping hierarchy to indicate a compressed state of the corresponding page; and

updating a compressed page mapping hierarchy to indicate the physical address and size of the corresponding compressed representation.

20. A method for handling a compression fault, as recited in claim 19, comprising the additional steps of:

mapping to the uncompressed representation in memory using the virtual address of the faulting memory access supplied in the virtual address supplying step, a portion of the virtual address indexing into a corresponding translation lookaside buffer entry, wherein the translation lookaside buffer entry includes base address in memory of the uncompressed representation of the page corresponding to the virtual address;

compressing the page identified in the uncompressed representation mapping step into the new block in the compressed memory space; and

returning a size of the compressed representation.

21. A method for handling a compression fault, as recited in claim 19, wherein the physical address supplying step and the virtual address supplying step include pushing the physical address and the virtual address to a stack, and wherein the size returning step includes storing the size of the compressed representation to a control register.