Power management system for components used in battery powered applications

• US 5,696,977 A
• Filed: 03/25/1996
• Issued: 12/09/1997
• Est. Priority Date: 02/19/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven E., Garner, Richard, Kendall, Terry L., Kynett, Virgil Niles
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/621,248
• Time in Patent Office: 624 Days
• Field of Search: 395/750, 395/550, 395/555, 395/560, 364/707
• US Class Current: 713/322
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the component circuit, timing apparatus for sensing a period during which the component circuit has not performed an operation, and apparatus for disabling the gating apparatus for providing the square wave pulses at an output terminal.

Claims

1. An apparatus for use with a computer component circuit, the apparatus comprising:

a microprocessor;

an oscillator for providing a pattern of signals;

a clock signal generator, coupled to the oscillator, for generating clock pulses based on the pattern of signals; and

wherein the microprocessor is for running a first process to selectively disable the oscillator and the clock signal generator at the completion of any operation by the component circuit.

2. The apparatus of claim 1, further comprising:

a plurality of gates coupled to the oscillator and the clock signal generator; and

wherein the microprocessor is for running the first process to selectively disable the oscillator and the clock signal generator by controlling the plurality of gates.

3. The apparatus of claim 1, wherein the microprocessor is also for running a second process to enable the oscillator and the clock signal generator in response to any command to the component circuit from a host computer.

4. A computer subsystem comprising:

a microprocessor for managing the subsystem;

an oscillator for generating a pattern of signals;

a clock generator for providing clock signals based on the pattern of signals; and

a series of gates for selectively disabling the oscillator and the clock generator upon completion of any operation by the subsystem.

5. The computer subsystem of claim 4, wherein the series of gates is also for enabling the oscillator and the clock signal generator in response to any command to the subsystem from a host computer.

6. A computer system comprising:

a central processing unit;

a main memory;

a bus coupled to the central processing unit and the main memory; and

a subsystem coupled ot the bus, the subsystem comprising,

a control circuit that includes

a microprocessor for managing the subsystem,

an oscillator for generating a pattern of signals,

a clock generator for providing clock signals based on the pattern of signals, and

a series of gates for selectively disabling the oscillator and the clock generator upon completion of any operation by the subsystem, and for enabling the oscillator and the clock generator in response to any command to the subsystem from the central processing unit.

7. A method for controlling the use of power in a computer subsystem, the computer subsystem including a microprocessor for managing the subsystem, an oscillator for generating a pattern of signals, and a clock generator for providing clock signals based on the pattern of signals, the method comprising the step of:

selectively disabling the oscillator and the clock generator in response to commands from the microprocessor after the termination of any operation received from a host computer.

8. An apparatus for use with a computer component circuit, the apparatus comprising:

a means for providing a repeating pattern of signals;

a means for generating clock pulses based on the repeating pattern of signals; and

means for selectively disabling the means for providing and the means for generating at the completion of any operation by the component circuit.

9. The apparatus of claim 8, further comprising means for enabling the means for providing and the means for generating in response to any command to the component circuit from a host computer.