Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same

  • US 5,701,270 A
  • Filed: 02/01/1996
  • Issued: 12/23/1997
  • Est. Priority Date: 05/09/1994
  • Status: Expired due to Term
First Claim
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1. A memory subsystem comprising:

  • processing circuitry;

    first and second banks of memory, each said bank including a predetermined number of primary memory cells and a predetermined number of redundant memory cells;

    a primary address bus for allowing said processing circuitry to address at least one of said primary memory cells, said at least one primary memory cell residing in a primary cell memory space; and

    a redundancy bus for allowing said processing circuitry to address at least one of said redundancy cells, said at least one redundancy cell residing in a redundacy cell memory space separate from said primary cell memory space.

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