Semiconductor device having four power MOSFETs constituting H bridge circuit

• US 5,703,390 A
• Filed: 10/31/1995
• Issued: 12/30/1997
• Est. Priority Date: 10/31/1994
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Itoh, Yukio
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/550,863
• Time in Patent Office: 791 Days
• Field of Search: 257/335, 257/336, 257/337, 257/338, 257/340, 257/341, 257/343, 257/344, 257/401
• US Class Current: 257/337
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device including first, second, third and fourth MOSFETs constituting an H bridge circuit. Each of the first and second MOSFETs is a vertical DMOSFET and each of the third and fourth MOSFETs is a lateral DMOSFET having a surface diffusion region formed in a portion of a drain region. The surface diffusion region has a conductivity type opposite that of a source region of the lateral DMOSFET and is electrically connected to the source region. Each of the surface diffusion regions may be made of a part of a channel stop region formed under a field insulator film. Each of the third and fourth MOSFETs may be a lateral DMOSFET having no surface diffusion region. Low on-resistance and small chip size of the device are obtained.

Claims

1. A semiconductor device comprising:

first, second, third and fourth MOSFETs formed in a semiconductor substrate;

drains of said first and second MOSFETs being coupled together;

sources of said third and fourth MOSFETs being coupled together;

a source of said first MOSFET being connected to a drain of said third MOSFET;

a source of said second MOSFET being connected to a drain of said fourth MOSFET; and

said first, second, third and fourth MOSFETs constituting an H bridge circuit;

wherein said first and second MOSFETS are different in structure from said third and fourth MOSFETs.

2. A semiconductor device as claimed in claim 1, wherein each of said first and second MOSFETs is a vertical DMOSFET and each of said third and fourth MOSFETs is a lateral DMOSFET having a surface diffusion region formed in a portion of said a drain region of said third and fourth MOSFETs;

and wherein each of said surface diffusion regions have a conductivity type opposite that of a source region of said lateral DMOSFET and is electrically connected to said source region.

3. A semiconductor device as claimed in claim 2, wherein each of said surface diffusion regions is made of a part of a channel stop region formed under a field insulating film.

4. A semiconductor device as claimed in claim 1, wherein each of said first and second MOSFETs is a vertical DMOSFET and each of said third and fourth MOSFETs is a lateral DMOSFET.

5. A semiconductor device comprising:

(a) first, second, third and fourth MOSFETs formed in a semiconductor substrate of a first conductivity type;

a field insulating film formed on a first surface of said substrate to laterally isolate said first, second, third and fourth MOSFETs;

drains of said first and second MOSFETs being coupled together;

sources of said third and fourth MOSFETs being coupled together;

a source of said first MOSFET being connected to a drain of said third MOSFET;

a source of said second MOSFET being connected to a drain of said fourth MOSFET; and

said first, second, third and fourth MOSFETs constituting an H bridge circuit;

(b) each of said first and second MOSFETs being a vertical DMOSFET and each of said third and fourth MOSFETs being a lateral DMOSFET having a surface diffusion region formed in a portion of a drain region of said third and fourth MOSFETS;

(c) said vertical DMOSFET having;

a base region of a second conductivity type formed in said substrate, said second conductivity type being opposite to said first conductivity type;

a source region of said first conductivity type formed in said base region;

a gate insulator film formed on a first surface of said substrate;

a gate electrode formed on said gate insulator film;

a source electrode in contact with said source region;

a drain electrode formed on a second surface of said substrate;

(d) said lateral DMOSFET having;

a well region of a second conductivity type formed in said substrate, said second conductivity type being opposite to said first conductivity type;

a base region of said second conductivity type formed in said well region;

a source region of said first conductivity type formed in said base region;

a drain region of said first conductivity type formed in said well region;

a surface diffusion region of said second conductivity type formed in said drain region;

a gate insulator film formed on a first surface of said substrate;

a gate electrode formed on said gate insulator film;

a source electrode in contact with said source region;

a drain electrode in contact with said drain region;

said surface diffusion region being electrically connected to said source region.

6. A semiconductor device as claimed in claim 5, wherein each of said surface diffusion regions is made of a part of a channel stop region formed under said field insulating film.

7. A semiconductor device comprising:

(a) first, second, third and fourth MOSFETs formed in a semiconductor substrate of a first conductivity type;

a field insulating film formed on a first surface of said substrate to laterally isolate said first, second, third and fourth MOSFETS;

drains of said first and second MOSFETs being coupled together;

sources of said third and fourth MOSFETs being coupled together;

a source of said first MOSFET being connected to a drain of said third MOSFET;

a source of said second MOSFET being connected to a drain of said fourth MOSFET; and

said first, second, third and fourth MOSFETs constituting an H bridge circuit;

(b) each of said first and second MOSFETs being a vertical DMOSFET and each of said third and fourth MOSFETs being a lateral DMOSFET having a surface diffusion region formed in a portion of said a drain region of said third and fourth MOSFETs;

(c) said vertical DMOSFET having;

a base region of a second conductivity type formed in said substrate, said second conductivity type being opposite to said first conductivity type;

a source region of said first conductivity type formed in said base region;

a gate insulator film formed on said first surface of said substrate;

a gate electrode formed on said gate insulator film;

a source electrode in contact with said source region; and

a drain electrode formed on a second surface of said substrate; and

(d) said lateral DMOSFET having;

a well region of said second conductivity type formed in said substrate;

a base region of said second conductivity type formed in said well region;

a source region of said first conductivity type formed in said base region;

a drain region of said first conductivity type formed in said well region;

a gate insulator film formed on said first surface of said substrate;

a gate electrode formed on said gate insulator film;

a source electrode in contact with said source region; and

a drain electrode in contact with said drain region.