Power-on-reset and watchdog circuit and method

• US 5,704,038 A
• Filed: 04/17/1996
• Issued: 12/30/1997
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: ITT Automotive Electrical Systems, Inc. (ITT, Inc.)
• Original Assignee: ITT Automotive Electrical Systems, Inc. (ITT, Inc.)
• Inventors: Miciano, Benjamin L., Mueller, Donald L.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): VALES, PHILLIP
• Application Number:
  US08/632,328
• Time in Patent Office: 622 Days
• Field of Search: 395/185.08, 395/185.09, 371/61, 371/62
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A power-on-reset and watchdog circuit is disclosed which employs discrete bipolar transistors to provide reset capability for microprocessors in the event of power-up or microprocessor malfunction. The present invention has a watchdog detection circuit which monitors a pulsed microprocessor output signal. As long as the watchdog detection circuit receives the pulsed microprocessor output signal, the microprocessor will not reset. In the event of microprocessor malfunction the pulsed microprocessor output signal will latch either high or low, initiating an oscillator circuit to reset the microprocessor. Upon power-up, the watchdog detection circuit will be forced into the off state for a specified amount of time so as to invoke the oscillator circuit, thereby resetting the microprocessor.

Claims

1. A watchdog circuit for use in conjunction with a microprocessor having a reset input terminal and a watchdog output terminal comprising:

a monitor circuit comprising passive elements, and no more than one transistor, which monitors the watchdog output terminal of the microprocessor and generates a monitor error signal in response to detecting a malfunction signal on the watchdog output terminal;

a reset circuit having an input terminal and an output terminal, wherein

(1) the output terminal is connected to the reset input terminal of the microprocessor

(2) said reset circuit generates a reset signal on the output terminal of the reset circuit in response to receipt of the monitor error signal on the input terminal of the reset circuit, and

(3) the input terminal of the reset circuit is different from the output terminal of the reset circuit.

2. The watchdog circuit as recited in claim 1 wherein said monitor circuit comprises a transistor having an RC circuit coupled to the base thereof.

3. The watchdog circuit as set forth in claim 1 wherein said reset circuit comprises no more than two transistors configured with a plurality of capacitors to facilitate generating said reset signal.

4. The watchdog circuit as recited in claim 1 wherein said monitor circuit and said reset circuit are configured to generate an initializing reset signal when said microprocessor is initialized.

13. The watchdog circuit of claim 1, further comprising a uniform DC voltage source, wherein said reset circuit uses said uniform DC voltage source to generate the reset signal on the output terminal of said reset circuit.

14. The watchdog circuit of claim 13, wherein the uniform DC voltage source provides a constant five (5) volt signal to said reset circuit.

17. The watchdog circuit as recited in claim 3 wherein at least one of said plurality of transistors is coupled to said monitor circuit to permit said reset circuit to oscillate said monitor error signal.

5. A method for resetting a microprocessor having a reset input terminal and a watchdog output terminal, comprising the steps of:

detecting a microprocessor error signal on the watchdog output terminal of the microprocessor and generating an oscillating monitor error signal in response thereto;

detecting the oscillating monitor error signal at a first node and;

generating a reset enable signal at a second node in response thereto, wherein

(1) the second node is connected to the reset input terminal of the microprocessor, and

(2) the first node is different from the second node.

6. The method as recited in claim 5 wherein the step of detecting the monitor error signal at a first node and generating a reset enable signal at a second node in response thereto further comprises the stop of:

providing a watchdog monitor circuit comprising at least one transistor and a reset enable circuit comprising no more than two transistors which are coupled to generate the reset enable signal in response to said microprocessor error signal.

7. The method as recited in claim 5 wherein said method further comprises the step of:

generating said microprocessor error signal upon initialization of said microprocessor.

8. The method as recited in claim 5 wherein the step of detecting the monitor error signal at a first node and generating a reset enable signal at a second node in response thereto further comprises the steps of:

reverse biasing one transistor in response to said microprocessor error signal; and

forward biasing at least one other transistor.

15. The method of claim 5, wherein the step of detecting the monitor error signal at a first node and generating a reset enable signal at a second node in response thereto includes the steps of:

providing a uniform DC voltage; and

using the uniform DC voltage to generate the reset enable signal at the second node.

16. The method of claim 15, wherein the uniform DC voltage is five (5) volts.

18. The method as recited in claim 5 wherein the step of detecting the monitor error signal at a first node and generating a reset enable signal at a second node in response thereto comprises the step of:

oscillating said reset enable signal.

9. A method of resetting a microprocessor having an input terminal and an output terminal, comprising the steps of:

detecting a microprocessor error signal on the output terminal of the microprocessor with a watchdog monitor circuit and generating a monitor error signal in response thereto;

detecting the monitor error signal on an input terminal of a reset enable circuit and generating a reset enable signal on an output terminal of the reset enable circuit in response thereto, wherein (1) the output terminal of the reset enable circuit is connected to the input terminal of the microprocessor, and (2) the input terminal of the reset enable circuit is different from the output terminal of the reset enable circuit.

10. The method of claim 9 further comprising the step of:

generating the microprocessor error signal on the output terminal of the microprocessor when the microprocessor is initialized.

11. The method of claim 9, wherein the step of detecting the monitor error signal on an input terminal of a reset enable circuit and generating a reset enable signal on an output terminal of the reset enable circuit in response thereto includes the steps of:

providing a uniform DC voltage to the reset enable circuit; and

using the uniform DC voltage to generate the reset enable signal on the output terminal of the reset enable circuit.

12. The method of claim 11, wherein the uniform DC voltage is five (5) volts.

19. A circuit, comprising:

a) a microprocessor having

i) a reset input (50) and;

ii) an error output (60), which outputs a pulse train in the absence of an error condition;

b) an oscillator,

i) comprising

A) a transistor network for delivering an oscillating signal to said reset input (50);

B) a monitor means which detects said pulse train and, in response, inhibits the transistor network from oscillating.

20. Circuit according to claim 19, wherein the oscillator is effective to produce said oscillating signal without an oscillating input.

21. Circuit according to claim 19, wherein the oscillator is effective to produce said oscillating signal when all signal inputs and all power inputs to the oscillator are of the DC type.

22. A circuit for applying pulses to a first pin (50) of a microprocessor, when the microprocessor ceases producing pulses at a second pin (60), comprising:

a) three transistors; and

b) circuit means, which includes resistors and capacitors, comprising

i) nodes N1 and N2, connected to a first of said transistors;

ii) nodes N2 and N3, connected to a second of said transistors;

iii) nodes N5 and N7, connected to a third of said transistors;

iv) a connection for applying signals at node N3 to said first pin (50); and

v) a connection for applying signals at said second pin (60) to node N1,

wherein a train of pulses is produced at node N3 when a train of pulses at node N1 terminates.

23. An electronic circuit, comprising:

a) a microprocessor (40), having a reset input (50) and an error output (60);

b) a monitoring-and-reset circuit, consisting essentially of the following;

i) a power line and a ground line;

ii) a first resistor (R1) connecting between a node N1 and the ground line;

iii) a first NPN transistor (Q1), having

A) its base connected to the node N1;

B) its collector connected to a node N2;

C) its emitter connected to the around line;

iv) a parallel RC network (R2, C1), connecting between the node N2 and the power line;

v) a second NPN transistor (Q2), having

A) its base connected to the node N2;

B) its collector connected to a node N3;

C) its emitter connected to the ground line;

vi) a third resistor (R3) connecting between the node N3 and the power line;

vii) a second capacitor (C2) connecting between the node N3 and the ground line;

viii) a fourth resistor (R4) connecting between the node N3 and a node N7;

ix) a PNP transistor (Q3), having

A) its base connected to the node N7;

B) its collector connected to a node N5;

C) its emitter connected to the power line;

x) a fifth resistor (R5), connecting between the node N5 and the ground line;

xi) a sixth resistor (R6), connecting between the node N5 and a node N6;

xii) a third capacitor (C3), connecting between the node N6 and the ground line;

xiii) a seventh resistor (R7), connecting between the node N6 and the node N1;

xiv) a fourth capacitor (C4), connecting between the node N1 and the error output (60); and

xv) a line connecting between node N3 and the reset input (50),

wherein node N3 delivers an oscillating signal to the reset input (50) in the absence of a pulse train at the error output (60), and wherein node N3 delivers a DC signal to the reset input (50) when a pulse train exists at the error output (60).