Data processing system for processing one and two parcel instructions

• US 5,717,881 A
• Filed: 06/07/1995
• Issued: 02/10/1998
• Est. Priority Date: 12/29/1989
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Beard, Douglas R., Phelps, Andrew E., Woodmansee, Michael A., Blewett, Richard G., Lohman, Jeffrey A., Silbey, Alexander A., Spix, George A., Simmons, Frederick J., Van Dyke, Don A.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/481,060
• Time in Patent Office: 979 Days
• Field of Search: 395/380, 395/381, 395/384, 395/390
• US Class Current: 712/205
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8076 Details on data register access
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 : Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 : Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3846 : using static prediction, e.g. branch taken strategy
• CPC Class Codes: G06F 9/3856 : Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3875 : Pipelining a single stage, e.g. superpipelining
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

An improved high performance hardwired supercomputer data processing apparatus includes instruction means adpated to issue one and two parcel instructions. Instruction fetch means provides an instruction stream of two parcel items in sequence. Instruction decode means is responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction or two one parcel instructions, for issuing each two parcel instruction for execution during the one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during the one clock cycle and the next succeeding clock cycle.

Claims

1. A hardwired supercomputer data processing apparatus comprising:

instruction fetch means for providing an instruction stream of two parcel items in sequence, wherein each two parcel item has a bit length of 2n;

instruction decode means responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction having a bit length of 2n bits or two one parcel instructions, each having a bit length of n bits; and

instruction issue means responsive to the instruction decode means for issuing each two parcel instruction for execution during said one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during said one clock cycle and the next succeeding clock cycle.