Data processing system for processing one and two parcel instructions

  • US 5,717,881 A
  • Filed: 06/07/1995
  • Issued: 02/10/1998
  • Est. Priority Date: 12/29/1989
  • Status: Expired due to Term
First Claim
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1. A hardwired supercomputer data processing apparatus comprising:

  • instruction fetch means for providing an instruction stream of two parcel items in sequence, wherein each two parcel item has a bit length of 2n;

    instruction decode means responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction having a bit length of 2n bits or two one parcel instructions, each having a bit length of n bits; and

    instruction issue means responsive to the instruction decode means for issuing each two parcel instruction for execution during said one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during said one clock cycle and the next succeeding clock cycle.

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