Circuit for selecting and designating a master battery pack in a computer system

• US 5,717,937 A
• Filed: 03/04/1996
• Issued: 02/10/1998
• Est. Priority Date: 03/04/1996
• Status: Expired due to Term

• Current Assignee: HTC Corporation
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Fritz, Brian C.
• Primary Examiner(s): Ray, Gopal C.
• Time in patent office: 708 Days
• Field of Search: 395/750, 320/6, 320/15, 320/39, 320/5, 320/30, 307/66, 364/492, 364/707, 365/226, 365/229
• US Class Current: 713/300
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: H02J 7/00036 Charger exchanging data with battery
• CPC Class Codes: H02J 7/00047 with provisions for charging different types of batteries

Abstract

The present invention relates to circuitry for selecting a master battery pack for supplying power to a computer system capable of incorporating multiple battery packs. A bi-directional master battery signal is communicated to the microcontroller of each installed battery pack and arbitration circuitry contained within the host computer system. The master battery signal operates in conjunction with a serial communications interface between each of the installed battery packs and the host computer system. Battery status information is communicated to the host computer system via the serial communications interface, and the host computer system then selects a master battery pack. The battery pack selected to be the master asserts the master battery signal while all other battery packs monitor this signal waiting for it to be deasserted. Other battery packs utilize the master battery signal to control their own charge and discharge circuitry. Deassertion of the master battery signal denotes that the master battery pack is no longer capable of supplying power to the host computer system and the master battery pack arbitration process is repeated.

Claims

1. A battery pack for providing power to a host computer system with battery pack arbitration circuitry, said battery pack comprising:

battery pack terminals;

battery cells;

discharge enabling circuitry coupled to said battery pack terminals and said battery cells, said discharge enabling circuitry when enabled permitting discharge of said battery cells through said battery pack terminals and otherwise blocking discharge of said battery cells; and

data processing circuitry electrically coupled to said discharge enabling circuitry, said data processing circuitry comprising;

a serial bus interface for communicating battery status information to the battery pack arbitration circuitry of the host computer system and for receiving selection commands from the battery pack arbitration circuitry of the host computer system;

a master battery signal line interface for communicating a master battery signal;

logic responsive to said master battery signal and responsive to selection commands received over said serial bus interface for controlling said discharge enabling circuitry; and

logic for selectively providing said master battery signal responsive to selection commands received over said serial bus interface.

2. The battery pack of claim 1, wherein said logic responsive to said master battery signal and responsive to selection commands received over said serial bus interface activates said discharge enabling circuitry when said master battery signal indicates that the battery pack arbitration circuitry of the host computer system has not selected a master battery pack.

3. The battery pack of claim 1, wherein said logic responsive to said master battery signal and responsive to selection commands received over said serial bus interface deactivates said discharge enabling circuitry when said master battery signal indicates that the battery pack arbitration circuitry of the host computer system has selected another source of power to serve as the master battery.

4. The battery pack of claim 1, wherein said logic for selectively providing said master battery signal responsive to selection commands received over said serial bus interface asserts said master battery signal when the selection commands indicate said battery pack is the master battery pack.

5. The battery pack of claim 1, further comprising charge enabling circuitry electrically coupled to said data processing circuitry, said battery cells, and said battery pack terminals.

6. The battery pack of claim 5, wherein said logic responsive to said master battery signal and responsive to selection commands received over said serial bus interface also controls said charge enabling circuitry, and wherein said logic activates said charge enabling circuitry when the selection commands indicate said battery pack is the master battery pack.

7. The battery pack of claim 1, wherein said serial bus interface is compliant with the I² C-bus specification.

8. The battery pack of claim 1, further comprising battery pack identification means electrically coupled to said data processing circuitry, said identification means being capable of providing information for determining battery pack location within the host computer system.

9. The battery pack of claim 8, wherein said battery pack identification means comprise circuitry capable of connecting to and discerning the ohmage of an identification resistor within the host computer system.

10. The battery pack of claim 1, further comprising sensor circuitry electrically coupled to said data processing circuitry for determining and providing battery cell status information.

11. A computer system capable of being powered by battery packs, said computer system comprising:

at least one battery pack interface;

battery pack arbitration circuitry coupled to said at least one battery pack interface;

a serial bus for communicating battery pack status information from said at least one battery pack interface to said battery arbitration circuitry and for communicating commands from said battery arbitration circuitry to said at least one battery pack interface for selecting a battery pack connected to said at least one battery pack interface; and

a master battery signal line for communicating a master battery signal from said at least one battery pack interface to said battery arbitration circuitry, said master battery signal indicating whether a battery pack is functioning as a master battery pack to supply power to said computer system.

12. The computer system of claim 11, wherein said battery pack arbitration circuitry selects a master battery pack based on the amount of charge stored in each installed battery pack as determined by battery pack status information communicated via said serial bus.

13. The computer system of claim 11, wherein said at least one battery interface includes a plurality of battery interfaces, said computer system further comprising means for determining if a battery is connected to each battery interface of said plurality of battery interfaces.

14. The computer system of claim 11, wherein said battery pack arbitration circuitry selects a master battery pack from battery packs determined to be connected to said plurality of battery interfaces, said selection based on a predetermined ordering of battery interfaces in said plurality of battery interfaces.

15. The computer system of claim 11, wherein said serial bus interface is compliant with the I² C-bus specification.

16. The computer system of claim 11, further comprising:

means for detecting the presence of alternating current power and providing a signal to said master battery signal line preventing the discharge of batteries upon detection of alternating current power.

17. A combination of a host computer system and at least one battery pack, the combination comprising:

a master battery signal line for communicating a master battery signal indicating whether the at least one battery pack is supplying power to a host computer system;

a serial bus;

the host computer system having battery pack arbitration circuitry, said battery pack arbitration circuitry being electrically coupled to said serial bus in order to receive battery pack status information and to communicate commands for selecting a master battery pack, said battery pack arbitration circuitry further being electrically coupled to said master battery signal line in order to receive the master battery signal; and

said at least one battery pack installed in said host computer system, said at least one battery pack comprising;

battery pack terminals;

battery cells;

discharge enabling circuitry coupled to said battery pack terminals and said battery pack cells, said discharge enabling circuitry when enabled permitting discharge of said battery cells through said battery pack terminals and otherwise blocking discharge of said battery cells;

data processing circuitry electrically coupled to said discharge enabling circuitry, said master battery signal line, and said serial bus, said data processing circuitry comprising;

logic responsive to the master battery signal and responsive to selection commands received over said serial bus for controlling said discharge enabling circuitry; and

logic for selectively providing the master battery signal in response to selection commands received over said serial bus.

18. The combination of claim 17, wherein said logic responsive to the master battery signal and responsive to selection commands received over said serial bus activates said discharge enabling circuitry when the master battery signal indicates that said battery pack arbitration circuitry of said host computer system has not selected a master battery pack.

19. The combination of claim 17, wherein said logic responsive to the master battery signal and responsive to selection commands received over said serial bus deactivates said discharge enabling circuitry when the master battery signal indicates that said battery pack arbitration circuitry of said host computer system has selected another source of power to be the master battery.

20. The combination of claim 17, wherein in a particular one of said at least one battery pack, said logic for selectively providing the master battery signal in response to selection commands received over said serial bus asserts the master battery signal when the selection commands indicate said particular one of said at least one battery pack is the master battery pack.

21. The combination of claim 17 wherein said at least one battery pack further comprises charge enabling circuitry electrically coupled to said data processing circuitry, said battery cells, and said battery pack terminals.

22. The combination of claim 21, wherein in a particular one of said at least one battery pack said logic responsive to said master battery signal and responsive to selection commands received over said serial bus also controls said charge enabling circuitry, and wherein said logic activates said charge enabling circuitry when the selection commands indicate said particular one of said at least one battery pack is the master battery pack.

23. The combination of claim 17, wherein said serial bus is compliant with the I² C-bus specification.

24. The combination of claim 17, further comprising battery pack identification means electrically coupled to said data processing circuitry, said identification means being capable of providing information for determining battery, pack location within said host computer system.

25. The combination of claim 24, wherein said battery pack identification means comprise circuitry connecting to and discerning the ohmage of an identification resistor within the host computer system.

26. The combination of claim 17, wherein said battery pack arbitration circuitry selects one of said at least one battery pack to be the master battery pack based on the amount of charge stored in each of said at least one battery pack.

27. The combination of claim 17, further comprising:

means for detecting the presence of alternating current power and providing a signal to said master battery signal line upon detection of alternating current power.

28. A method for selecting a master battery pack for supplying power to a host computer system capable of incorporating at least one battery pack, said host computer system having no current master battery pack, said method comprising the steps of:

determining that no battery pack is currently serving as the master battery pack by examining the voltage level of a master battery signal line linking the host computer system to installed battery packs;

determining the charge status of any battery packs installed in the host computer system via communications over a serial bus interface between the host computer system and installed battery packs;

selecting a master battery pack based on predetermined selection criteria; and

communicating the selection to the new master battery pack via further communications over the serial bus interface.

29. The method of claim 28, further comprising the step of:

communicating the selection of the master battery pack to any other installed battery packs by providing an appropriate signal on the master battery signal line.

30. The method of claim 29, further comprising the step of:

signalling the host computer system of the presence of a newly installed battery pack via communications over the serial bus interface if the voltage level of the master battery signal line indicates that no battery pack is currently serving as the master battery pack.

31. The method of claim 28, the method further comprising the step of:

prior to said step of determining that no battery pack is currently serving as the master battery pack, causing the voltage level of the master battery signal line to transition to a level indicating that the prior master battery pack has either been removed from the host computer system or is no longer the preferred source of power to the computer system.