Packet-based dynamic de-skewing for network switch with local or central clock

• US 5,719,862 A
• Filed: 05/14/1996
• Issued: 02/17/1998
• Est. Priority Date: 05/14/1996
• Status: Expired due to Fees

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Lee, Raymond K., Hui, Alex Chi-Ming
• Primary Examiner(s): HSU, ALPUS
• Application Number:
  US08/649,114
• Time in Patent Office: 644 Days
• Field of Search: 370/218, 370/250, 370/252, 370/253, 370/355, 370/357, 370/359, 370/360, 370/388, 370/389, 370/400, 370/445, 370/447, 370/461, 370/503, 370/505, 370/506, 370/514, 370/516, 370/520, 340/825.03, 340/826, 340/827, 340/825.79, 340/825.8, 375/362, 375/364, 375/371
• US Class Current: 370/355
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane

Abstract

A network switch uses a simple switch core of analog MOS transistor switches. The switch core is surrounded by many media-access controllers (MAC'"'"'s) which buffer the data through the switch core. Multiple connections through the switch core may be made between different pairs of MAC'"'"'s. Just one signal path through the switch core is needed per connection as a second path through the switch core for the clock is not needed. The clock is not encoded with the data, so PLL'"'"'s are not needed for clock recovery. Data skew is instead measured for each packet transmitted through the switch core. A start flag is added to the packet by a source MAC as a packet header before being transmitted through the switch core. The start flag is a unique sequence which is detected by the destination MAC and triggers measurement of the data skew of the received start flag to the local clock. The measured data skew is then used to compensate for the rest of the packet. Because dynamic de-skewing is performed for each packet, any packet from any source MAC can be received. This allows freedom in MAC placement and enables construction of larger switches. The switch may have the MAC'"'"'s physically separated from each other by greater distances since clocks can be locally generated. The clocks are independent from each other except for having the same frequency.

Claims

1. A network switch comprising:

a switch core having a plurality of input ports and a plurality of output ports, the switch core for establishing a plurality of temporary connections, each temporary connection between an input port and an output port;

a plurality of media-access-controller (MAC) modules, including source MAC modules and destination MAC modules;

each source MAC module in the plurality of MAC modules connected to an external network node for receiving data packets from the external network node, the source MAC module connected to an input port on the switch core;

a packet framer in each source MAC module for adding a start flag to a beginning of a data packet before the data packet with the start flag is transmitted to the switch core;

each destination MAC module in the plurality of MAC modules connected to an external network node for transmitting data packets to the external network node from the network switch, the destination MAC module connected to an output port on the switch core;

packet de-skew means in each destination MAC module for measuring a skew in the start flag of each packet received from the switch core and compensating the data packet for the measured skew;

whereby each data packet transmitted through the switch core is compensated for skew by measuring the skew of the start flag transmitted with the data packet.

2. The network switch of claim 1 wherein the start flag is a unique bit pattern not appearing in the data packet.

3. The network switch of claim 2 further comprising:

encoding means, in the source MAC module, for modifying the data packet to prevent the unique bit pattern of the start flag from appearing in the data packet transmitted through the switch core;

decoding means, in the destination MAC module, for reversing any modifications made by the encoding means to the data packet transmitted through the switch core to re-generate the data packet,

whereby the data packet is modified before transmission through the switch core to modify any instance of the unique bit pattern of the start flag appearing in the data packet.

4. The network switch of claim 3 wherein the encoding means comprises zero-insertion means for inserting a zero bit after a sequence of ones in the data packet, the sequence of ones being a sequence of one less bit than in the unique bit pattern of the start flag, and wherein the decoding means comprises zero stripping means for removing an inserted zero after the sequence of ones in the data packet transmitted through the switch core.

5. The network switch of claim 1 wherein the packet de-skew means comprises a de-skew circuit in the destination MAC module including:

detect means for detecting the start flag at the beginning of the data packet;

variable delay means for adding a variable delay to the data packet;

skew measure means for measuring the skew between bit-transitions in the data packet received by the de-skew circuit, the skew measured relative to a receive clock for clocking the destination MAC module;

select means, coupled to the skew measure means and the variable delay means, for selecting as the variable delay an amount of delay to compensate for the skew measured by the skew measure means,

whereby the de-skew circuit selects the variable delay added to the data packet to compensate for the measured skew.

6. The network switch of claim 5 further comprising:

a central clock source for generating the receive clock to the destination MAC module and for generating a transmit clock to the source MAC module,

wherein the skew is measured for the start flag transmitted by the source MAC module in synchronization to the transmit clock, the skew measured relative to the receive clock,

whereby a central clock source is used for the source MAC module and the destination MAC module.

7. The network switch of claim 5 further comprising:

a receive clock source for generating the receive clock to the destination MAC module;

a transmit clock source for generating a transmit clock to the source MAC module;

wherein the skew is measured for the start flag transmitted by the source MAC module in synchronization to the transmit clock, the skew measured relative to the receive clock,

wherein the transmit clock is independently generated from the receive clock from different clock sources, the transmit clock and the receive clock having substantially a same frequency but the transmit clock having an arbitrary phase relationship to the receive clock;

whereby a local clock source generates the source MAC module and a different local clock source generates the destination MAC module.

8. The network switch of claim 1 wherein the switch core comprises:

matrix of transistor switches, a transistor switch establishing a temporary connection when its gate is activated, the transistor switch having a source connected to an input port and a drain connected to an output port,

whereby the switch core comprises transistor switches.

9. The network switch of claim 8 wherein the temporary connection through the switch core is absent any active buffering,

whereby a simple transistor switch is used to conduct from the input port to the output port.

10. A switch for making multiple, simultaneous connections between nodes on a network, the switch comprising:

a switch-matrix core having a plurality of ports, the switch-matrix core establishing connections between the ports for analog transmission of data packets;

a plurality of framers, coupled to ports on the switch-matrix core, each framer for transmitting a flag header immediately before each data packet transmitted to a port of the switch-matrix;

a skew detector, coupled to a port of the switch-matrix core, for determining an amount of clock skew of a data packet transmitted through the switch-matrix core;

a skew compensator, coupled to the skew detector and coupled to the port of the switch-matrix core, for adding a delay to the data packet transmitted through the switch core, the delay being determined by the skew detector;

a plurality of media-access controllers (MAC'"'"'s), each MAC connected to a node on the network for driving and receiving physical signals of a data packet;

each MAC including means for transmitting the data packet received from the node on the network to the framer and means for receiving a data packet from the skew compensator and re-transmitting the data packet to the node on the network,

whereby skew is detected and compensated for.

11. The switch of claim 10 further comprising:

a switch controller, coupled to the switch-matrix core, for receiving a request and a destination address from a source MAC, the switch controller requesting a connection between a first port coupled to the source MAC and a second port connected to a destination MAC, the destination MAC being identified by the destination address;

arbitration means, within the switch controller, for selecting the request from the source MAC from a plurality of simultaneous requests from MAC'"'"'s,

whereby the switch controller arbitrates requests for the switch-matrix core.

12. The switch of claim 11 wherein the switch-matrix core comprises an integrated circuit (IC), the ports on the switch-matrix comprising pins on the IC, and wherein the switch controller comprises a separate IC,

whereby the switch-matrix core is a separate IC than the switch controller.

13. The switch of claim 12 wherein the switch-matrix core further comprises:

a plurality of activity detectors for detecting an absence of signal transitions on a port;

tear-down means, responsive to the plurality of activity detectors, for disabling a connection between a first port and a second port when an absence of signal transitions is detected on the first port;

busy signal means, responsive to the switch controller requesting a connection between the first port and the second port, for signaling to the switch controller that the connection cannot be made when either the first port or the second port is not idle,

whereby idle connections are closed by the switch-matrix core.

14. The switch of claim 11 wherein the connection between the first port coupled to the source MAC and the second port connected to a destination MAC comprises a single signal path through the switch-matrix core for uni-directional operation, or two signal paths through the switch-matrix core for full duplex communication between the source MAC and the destination MAC.

15. The switch of claim 11 wherein the plurality of MAC'"'"'s include MAC'"'"'s using a first protocol and MAC'"'"'s using a second protocol,

whereby the switch is a multi-protocol switch.

16. The switch of claim 15 further comprising a shared buffer for buffering the data packet, the shared buffer shared by a plurality of MAC'"'"'s.

17. The switch of claim 15 wherein the first protocol is a 10BaseT protocol and the second protocol is a 100BaseT protocol, wherein the second protocol transmits data at a rate substantially ten times the rate of the first protocol.

18. The switch of claim 15 wherein the first protocol is an Ethernet protocol and the second protocol is an asynchronous-transfer mode (ATM) protocol.

19. A network switcher for connecting nodes on a network, the network switcher comprising:

a switch core comprising a plurality of transistors and a plurality of ports, a transistor in the plurality of transistors forming a connection path from a first port to a second port when a gate electrode of the transistor is activated, the connection path being formed by the transistor conducting current from the first port to the second port when the gate electrode is activated;

a path decoder, receiving a source port identifier for indicating a source port and a destination port identifier for indicating a destination port, for determining which single transistor in the plurality of transistors forms a connection path between the source port and the destination port, the path decoder activating the gate electrode for the single transistor to form the connection path;

a start-flag generator, for generating a unique sequence of serial bits as a start flag;

buffer means, coupled to a node on the network, for receiving a serial data stream from the node and storing the serial data stream;

request means, coupled to the buffer means, for sending the source port identifier and the destination port identifier to the path decoder when a serial data stream is received by the buffer means;

frame means, receiving the serial data stream from the buffer means, for transmitting the start flag followed by the serial data stream to the source port of the switch core in a serial format;

flag detect means, coupled to the destination port, for detecting the start flag transmitted through the switch core to the destination port;

skew measurement means, responsive to the flag detect means, for comparing a phase of a local clock to a phase of bit-transitions in the start flag and indicating a selected delay of the start flag causing the phase of the local clock to match the phase of the bit-transitions in the start flag;

delay means, receiving the serial data stream from the destination port, for adding the selected delay to each bit-transition in the serial data stream to generate a compensated data stream;

output means, for transmitting the compensated data stream to a destination node on the network,

whereby skew of the start flag transmitted through the switch core is measured and used to compensate the serial data stream.

20. The network switcher of claim 19 wherein the serial data stream is a packet having a source address, a destination address, and a data field,

whereby skew is measured for each packet transmitted through the switch core.

21. The network switcher of claim 20 wherein the frame means includes NRZI means for converting the serial data stream and the start flag into NRZI format to generate bit-transitions for each period of a clock.