Method and apparatus for reducing power consumption in a computer system by placing the CPU in a low power mode

• US 5,721,937 A
• Filed: 03/03/1997
• Issued: 02/24/1998
• Est. Priority Date: 01/10/1994
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Insley, Mark W., Kurihara, Steven M.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Seto, Jeffrey K.
• Application Number:
  US08/810,548
• Time in Patent Office: 358 Days
• Field of Search: 395/750.02, 395/750.03, 395/750.04, 395/750.05
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system including a central processing unit (CPU) and a power management circuit (PMC). The CPU has an active mode where it is responsive to interrupt and direct memory access requests, and a standby mode where it is in a low power state and is not responsive to the interrupts and direct memory access requests. The PMC monitors the interrupts and direct memory access requests in the system when the CPU is in the standby mode, and causes the CPU to enter the active mode upon the detection of either an interrupt or a direct memory access request. The PMC includes: a standby register having a content which indicates either a standby or an active mode for the CPU; logic coupled to the standby register to produce a standby enabling output signal when the content of the standby register indicates a standby mode, and to produce a standby disabling output signal when the content of the standby register indicates an active mode; and logic which forces the content of the standby register to the active mode upon the detection of either an interrupt or a direct memory access request. A method for managing power consumed by a CPU of a computer system includes forcing the CPU to enter a low-power standby mode, monitoring the computer system for interrupts and direct memory access requests, and reactivating the central processing unit to an active mode where the CPU is capable of responding to the detected requests.

Claims

1. A computer system with power management comprising:

a central processing unit, said central processing unit having an active mode wherein it is responsive to external events, and a standby mode wherein power is maintained to said central processing unit and said central processing unit is in a low power state and is not responsive to said external events, said central processing unit operative such that whenever said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step, said central processing unit sets a condition indicating that said central processing unit is currently not required; and

a power management circuit coupled to said central processing unit, said power management circuit being operative to monitor for said external events when said central processing unit is in said standby mode, and to cause said central processing unit to enter said active mode upon the detection of an external event, said power management circuit being operative to force said central processing unit into said standby mode in response to the condition indicating that said central processing unit is currently not required.

2. A computer system as recited in claim 1 wherein said central processing unit has a standby input, and wherein said power management circuit has a standby output coupled to said standby input, said power management circuit being operative to enable said standby input to force said central processing unit into said standby mode, and to disable said standby input to force said central processing unit into said enabled mode.

3. A computer system as recited in claim 2 wherein said power management circuit is provided with a standby register, said standby register controlling said standby output and being coupled to said central processing unit by a bus, and wherein said central processing unit is operative to write to said standby register via said bus to force itself into said standby mode.

4. A computer system as recited in claim 1 wherein said central processing unit has an internal clock.

5. A computer system as recited in claim 4 wherein during said standby mode said internal clock is stopped.

6. A computer system as recited in claim 4 wherein during said standby mode said internal clock operates at a frequency slower than a normal operating frequency.

7. A computer system as recited in claim 4 wherein during said standby mode said internal clock operates at a normal operating frequency.

8. A computer system as recited in claim 1 wherein said external event includes an interrupt.

9. A computer system as recited in claim 1 wherein said external event includes a direct memory access request.

10. A computer system as recited in claim 1, wherein during said active mode said central processing unit periodically executes said series of basic housekeeping functions.

11. A method for managing power consumed by a computer system comprising the steps of:

forcing a central processing unit of a computer system to enter a low-power standby mode when said central processing unit has completed a series of basic housekeeping functions and a next operation to be performed by said central processing unit is a no operation idle step;

monitoring said computer system for external events to which said central processing unit should respond; and

reactivating said central processing unit to an active mode where said central processing unit is capable of responding to said external events.

12. A method as recited in claim 11 wherein said step of forcing a central processing unit of a computer system comprises the steps of:

said central processing unit writing a standby command to a standby register of a power management circuit which functions independently of said central processing unit; and

said power management circuit enabling a standby input of said central processing unit.

13. A method as recited in claim 12 wherein said step of monitoring said computer system comprises the steps of:

said power management circuit detecting at least one of an interrupt and a direct memory access request; and

writing an activate command to said standby register upon said detection.

14. A method as recited in claim 13 wherein said step of reactivating said central processing unit to a full-power mode comprises the step of said power management circuit disabling said standby input of said central processing unit.

15. A method as recited in claim 11 wherein said central processing unit includes an internal clock and said step of forcing a central processing unit of a computer system to enter a low-power standby mode includes stopping said internal clock.

16. A method as recited in claim 11 wherein said central processing unit includes an internal clock and said step of forcing a central processing unit of a computer system to enter a low-power standby mode includes the substep of inhibiting internal state transitions within said central processing unit while said internal clock is maintained at a normal operating frequency.

17. A method as recited in claim 11 further including the step of periodically executing said series of basic housekeeping functions when said central processing unit is in said active mode.

18. A method for managing power consumed by a computer system having a central processing unit, a power management device, and a peripheral device, wherein said power management device controls power to said peripheral device, the method comprising the steps of:

implementing a process on said computer system, said process having an executable instruction set for transferring data to said peripheral device; and

patching said process to modify a functionality of said process such that the execution of said executable instruction set for writing data to said peripheral device includes instructing said power management device to enable power to said peripheral device prior to transferring data to said peripheral device, transferring data to said peripheral device once said peripheral device has power, and then instructing said power management circuit to disable power to said peripheral device after the data transfer is complete.

19. A method for managing power consumed by a computer system as recited in claim 18, wherein said process is a device driver corresponding to said peripheral device.

20. A method for managing power consumed by a computer system as recited in claim 18, wherein said process is an operating system.