Clocked high voltage switch

• US 5,723,985 A
• Filed: 11/21/1995
• Issued: 03/03/1998
• Est. Priority Date: 11/21/1995
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Information Storage Devices, Inc. (Winbond Electronics Corporation)
• Inventors: Van Tran, Hieu, Blyth, Trevor, Simko, Richard T.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/590,267
• Time in Patent Office: 833 Days
• Field of Search: 326/68, 326/80-81, 326/83, 326/86, 326/121, 326/95, 326/98, 327/333, 327/390, 327/536, 327/589, 257/400-401, 257/399, 257/398
• US Class Current: 326/81
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.

Claims

1. A high voltage output level shifter using low voltage MOS devices comprising:

a first terminal for coupling to a first voltage source, a second terminal for coupling to a second voltage source, a third terminal for coupling to a third voltage source, a fourth terminal for coupling to a clock signal, and an output terminal, wherein said second voltage source is intermediate to said first and third voltage sources;

first, second, third and fourth devices, each having a source, a drain and a gate, said second device having a channel region between said source and drain of said second device, said second device having a field implant terminating short of said source and said drain of said second device, the field implant also terminating at the edge of said channel region, said drain of said first device being coupled to said first terminal, said source of said first device and said drain of said second device being coupled together, said source of said second device and said drain of said third device being coupled to said output terminal, said source of said third device and said drain of said fourth device being coupled together, said gate of said third device being coupled to said second terminal, said source of said fourth device being coupled to said third terminal;

an input circuit for providing an input signal;

a charge pump coupled to said input circuit and to said gates of said first and second devices for charging said gates of said first and second devices to a threshold voltage above that provided by said first voltage source in response to said input signal; and

a circuit coupled to said input circuit and to said gates of said third and fourth devices for switching said third and fourth devices off in response to said input signal.

2. The high voltage output level shifter of claim 1 wherein said input circuit further comprises first and second output terminals, said second output terminal providing a signal complementary to a signal provided by said first output terminal.

3. The high voltage output level shifter of claim 1 wherein said charge pump comprises:

a fifth terminal for coupling to a fourth voltage source;

fifth, sixth, seventh and eighth devices each having a gate, a drain and a source, said drain of said fifth device being coupled to said fifth terminal, said source of said fifth device being coupled to said drain of said sixth device, said gate and said drain of said seventh device being coupled to said source of said sixth device, said source of said seventh device being coupled to said gate of said fifth device and to said gate of said first device, said gate and said drain of said eighth device being coupled to said source of said sixth device, said source of said eighth device being coupled to said gate of said sixth device and to said gate of said second device; and

a capacitor having a first terminal and a second terminal, said first terminal of said capacitor being coupled to said fourth terminal and said second terminal of said capacitor being coupled to said gate and drain of said eighth device.

4. The high voltage output level shifter of claim 3, wherein said sixth, seventh and eighth devices each having a channel region between said source and drain, and a field implant terminating short of said source and said drain, the field implant also terminating at the edge of said channel region.

5. The high voltage output level shifter of claim 4 further comprising sixth and seventh terminals coupled to said gates of said first and second devices respectively, and to said sources of said seventh and eighth devices respectively, said sixth and seventh terminals being output terminals.

6. The high voltage output level shifter of claim 3, wherein said circuit comprises ninth, tenth and eleventh devices each having a source, a drain and a gate, said drain and said gate of said ninth device being coupled together and to said gate of said tenth device, said drain of said tenth device being coupled to said source of said eighth device, said gate of said tenth device being coupled to said second terminal, said source of said tenth device being coupled to said drain of said eleventh device, said source of said eleventh device being coupled to said third terminal, said gate of said eleventh device being coupled to said second output terminal of said input circuit.

7. The high voltage output level shifter of claim 3, further comprising a ninth device, having a gate, a drain and a source, said drain of said ninth device being coupled to said fourth terminal, said gate of said ninth device being coupled to said first output terminal of said input circuit and said source of said ninth device being coupled to said first terminal of said capacitor.

8. The high voltage output level shifter of claim 3, further comprising ninth and tenth devices, each having a gate, a drain and a source, said drain of said ninth device being coupled to said fourth terminal, said source of said ninth device being coupled to said first terminal of said capacitor, said gate of said ninth device being coupled to said drain of said tenth device, said source of said tenth device being coupled to said source of said eighth device, said gate of said tenth device being coupled to said second terminal.

9. The high voltage output level shifter of claim 3 further comprising a diode coupled between said first terminal and said gate of said fifth device, for limiting a maximum level of voltage at said sixth terminal.

10. The high voltage output level shifter of claim 2 wherein said input circuit comprises:

fifth and sixth devices of a first conductivity type, each having a drain, a source and a gate, said sources of said fifth and sixth devices being coupled together and to said second terminal, said gate of said fifth device being coupled to said drain of said sixth device, said gate of said sixth device being coupled to said drain of said fifth device, said source of said fifth device being coupled to a first output terminal;

seventh and eighth devices of a second conductivity type, each having a drain, a source and a gate, said drains of said seventh and eighth devices being coupled to said drains of said sixth and fifth devices respectively, said sources of said seventh and eighth devices being coupled to said third terminal, said drain of said seventh device being coupled to a second output terminal; and

an inverter having an output and an input, said output being coupled to said gate of said eighth device, said input being coupled to said gate of said seventh device and to an input terminal.

11. The input circuit of claim 10, wherein the first conductivity type is a p-channel device and the second conductivity type is an n-channel device.

12. The high voltage output level shifter of claim 1 wherein said first voltage source is approximately 21 volts and wherein said third voltage source is approximately 0 volts.

13. The high voltage output level shifter of claim 1 wherein said second voltage source is approximately eleven volts.

14. In a circuit having a plurality of series devices, a method of distributing a voltage among a plurality of devices, the method comprising the steps of:

(a) providing a first terminal for coupling to a first voltage source, a second terminal for coupling to a second voltage source, a third terminal for coupling to a third voltage source, a fourth terminal for coupling to a clock signal, and an output terminal, wherein said second voltage source is intermediate to said first and third voltage sources;

(b) providing first, second, third and fourth devices, each having a source, a drain and a gate, said second device having a channel region between said source and drain of said second device, said second device having a field implant terminating short of said source and said drain of said second device, the field implant also terminating at the edge of said channel region, said drain of said first device being coupled to said first terminal, said source of said first device and said drain of said second device being coupled together, said source of said second device and said drain of said third device being coupled to said output terminal, said source of said third device and said drain of said fourth device being coupled together, said gate of said third device being coupled to said second terminal, said source of said fourth device being coupled to said third terminal;

(c) providing an input circuit for providing an input signal;

(d) providing a charge pump coupled to said input circuit and to said gates of said first and second devices for charging said gates of said first and second devices to a threshold voltage above that provided by said first voltage source in response to an input signal; and

(e) providing a circuit coupled to said input circuit and to said gates of said third and fourth devices for switching said third and fourth devices off in response to said input signal.

15. The method of claim 14 wherein in step (c), said input circuit comprises first and second output terminals, said second output terminal providing a signal complementary to a signal provided by said first output terminal.

16. The method of claim 14 wherein in step (d), said charge pump comprises:

a fifth terminal for coupling to a fourth voltage source;

fifth, sixth, seventh and eighth devices each having a gate, a drain and a source, said drain of said fifth device being coupled to said fifth terminal, said source of said fifth device being coupled to said drain of said sixth device, said gate and said drain of said seventh device being coupled to said source of said sixth device, said source of said seventh device being coupled to said gate of said fifth device and to said gate of said first device, said gate and said drain of said eighth device being coupled to said source of said sixth device, said source of said eighth device being coupled to said gate of said sixth device and to said gate of said second device; and

a capacitor having a first terminal and a second terminal, said first terminal of said capacitor being coupled to said fourth terminal and said second terminal of said capacitor being coupled to said gate and drain of said eighth device.

17. The method of claim 16, wherein in step (d), said sixth, seventh and eighth devices each has a channel region between said source and drain, and a field implant terminating short of said source and said drain, the field implant also terminating at the edge of said channel region.

18. The method of claim 17, further comprising the step of providing sixth and seventh terminals coupled to said gates of said first and second devices respectively, and to said sources of said seventh and eighth devices respectively, said sixth and seventh terminals being output terminals.

19. The method of claim 16, wherein in step (e), said circuit comprises ninth, tenth and eleventh devices each having a source, a drain and a gate, said drain and said gate of said ninth device being coupled together and to said gate of said tenth device, said drain of said tenth device being coupled to said source of said eighth device, said gate of said tenth device being coupled to said second terminal, said source of said tenth device being coupled to said drain of said eleventh device, said source of said eleventh device being coupled to said third terminal, said gate of said eleventh device being coupled to said second output terminal of said input circuit.

20. The method of claim 16, further comprising the step of providing a ninth device, having a gate, a drain and a source, said drain of said ninth device being coupled to said fourth terminal, said gate of said ninth device being coupled to said first output terminal of said input circuit and said source of said ninth device being coupled to said first terminal of said capacitor.

21. The method of claim 16, further comprising the step of providing ninth and tenth devices, each having a gate, a drain and a source, said drain of said ninth device being coupled to said fourth terminal, said source of said ninth device being coupled to said first terminal of said capacitor, said gate of said ninth device being coupled to said drain of said tenth device, said source of said tenth device being coupled to said source of said eighth device, said gate of said tenth device being coupled to said second terminal.

22. The method of claim 16 further comprising the step of providing a diode coupled between said first terminal and said gate of said fifth device, for limiting a maximum level of voltage at said sixth terminal.

23. The method of claim 15 wherein the step of providing an input circuit comprises the steps of:

providing fifth and sixth devices of a first conductivity type, each having a drain, a source and a gate, said sources of said fifth and sixth devices being coupled together and to said second terminal, said gate of said fifth device being coupled to said drain of said sixth device, said gate of said sixth device being coupled to said drain of said fifth device, said source of said fifth device being coupled to a first output terminal;

providing seventh and eighth devices of a second conductivity type, each having a drain, a source and a gate, said drains of said seventh and eighth devices being coupled to said drains of said sixth and fifth devices respectively, said sources of said seventh and eighth devices being coupled to said third terminal, said drain of said seventh device being coupled to a second output terminal; and

providing an inverter having an output and an input, said output being coupled to said gate of said eighth device, said input being coupled to said gate of said seventh device and to an input terminal.

24. The method of claim 23, wherein in the step of providing said fifth and sixth devices, the first conductivity type is a p-channel device and wherein in the step of providing said seventh and eighth devices, the second conductivity type is an n-channel device.

25. The method of claim 14 wherein said first voltage source is approximately 21 volts and wherein said third voltage source is approximately 0 volts.

26. The method of claim 14 wherein said second voltage source is approximately eleven volts.