Method and apparatus for managing active power consumption in a microprocessor controlled storage device

• US 5,724,592 A
• Filed: 12/05/1996
• Issued: 03/03/1998
• Est. Priority Date: 03/31/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Garner, Richard P.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Seto, Jeffrey K.
• Application Number:
  US08/760,325
• Time in Patent Office: 453 Days
• Field of Search: 395/750, 395/430, 395/494, 364/707
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash electrically-erasable programmable read only memory (EEPROM) array and a method for allowing a host computer to detect a plurality of different power-expending modes into which a storage device may be placed for operation, to select a particular one of those modes to match the power abilities of the host computer, and then to place the storage device in the proper power mode of operation to best function with the host system.

Claims

1. A flash electrically-erasable programmable read only memory (EEPROM) device comprising:

a flash EEPROM array;

a memory which stores indications of power modes in which the flash EEPROM device can be read from or written to;

a configuration register which stores a power mode configuration value, provided by a host processor, which corresponds to one of the power mode indications stored in the memory; and

a microprocessor, responsive to commands from the host processor, for reading the configuration register and for controlling operations related to the flash EEPROM array in accordance with the power mode configuration value.

2. A flash EEPROM device as claimed in claim 1 further comprising a memory which stores processes for selecting a mode for accessing the flash EEPROM array during read and write operations in accordance with the power mode configuration values.

3. A flash EEPROM device as claimed in claim 2 in which the mode for accessing the flash EEPROM array during read and write operations selects bytewide or wordwide accesses.

4. A flash EEPROM device as claimed in claim 1 further comprising a memory which stores processes for selecting operations which may be run concurrently by the flash EEPROM device in accordance with the power mode configuration values.

5. A flash EEPROM device as claimed in claim 1 further comprising a memory which stores processes for selecting a clock frequency for the microprocessor in accordance with the power mode configuration values.

6. A flash EEPROM device as claimed in claim 1 in which the microprocessor is also for controlling reading from and writing to the flash EEPROM array in each of the power modes in which the flash EEPROM device can be read from or written to.

7. A flash EEPROM device as claimed in claim 1, wherein:

said microprocessor selects a clock signal for the operations related to said flash EEPROM array, and wherein said clock signal is selectably divided from a system clock signal in accordance with said power mode configuration values.

8. A flash EEPROM device as claimed in claim 1, wherein:

said microprocessor selects either a byte-wide or a word-wide access mode for operations related to said flash EEPROM array in accordance with said power mode configuration values.

9. A microprocessor controlled storage device comprising:

memory array means;

microprocessor means, external to the memory array means, for controlling operations related to the memory array means;

means for storing indications of power modes in which the storage device can be read from or written to;

means for detecting indications, from a host processor, of power modes available;

means for setting a power mode configuration which corresponds to one of the power mode indications stored in the means for storing; and

means for responding to a set power mode configuration and for reducing power use of individual components of the storage device in accordance with the set power mode configuration.

10. A microprocessor controlled storage device as claimed in claim 9 in which the means for storing indications of power modes comprises:

attribute memory storage means.

11. A microprocessor controlled storage device as claimed in claim 9 in which the means for responding includes firmware processes run by the microprocessor means.

12. A microprocessor controlled storage device as claimed in claim 11 in which the firmware processes run by the microprocessor means selects a clock frequency for operation of the microprocessor means.

13. A microprocessor controlled storage device as claimed in claim 11 in which the firmware processes run by the microprocessor means selects a mode for accessing the memory array means during read and write operations.

14. A microprocessor controlled storage device as claimed in claim 11 in which the firmware processes run by the microprocessor means selects which operations may be run concurrently by the storage device.

15. A computer system comprising:

a central processing unit;

a system bus;

main memory; and

a flash electrically-erasable programmable read only memory (EEPROM) device comprising;

a flash EEPROM array,

a memory which stores indications of power modes in which the flash EEPROM device can be read from or written to,

a configuration register which stores a power mode configuration value, provided by the central processing unit, which corresponds to one of the power mode indications stored in the memory, and

a microprocessor, responsive to commands from the central processing unit, for reading the configuration register and for controlling operations related to the flash EEPROM array in accordance with the power mode configuration value.

16. A computer system as claimed in claim 15 in which the flash EEPROM device further comprises a memory which stores processes for selecting a mode for accessing the flash EEPROM array during read and write operations in accordance with the power mode configuration values.

17. A computer system as claimed in claim 16 in which the mode for accessing the flash EEPROM array during read and write operations selects bytewide or wordwide accesses.

18. A computer system as claimed in claim 15 in which the flash EEPROM device further comprises a memory which stores processes for selecting operations which may be run concurrently by the flash EEPROM device in accordance with the power mode configuration values.

19. A computer system as claimed in claim 15 in which the flash EEPROM device further comprises a memory which stores processes for selecting a clock frequency for the microprocessor in accordance with the power mode configuration values.

20. A method of managing power in a microprocessor controlled storage device, the method comprising the steps of:

(a) identifying a plurality of operating power modes in which the storage device can be read from or written to;

(b) selecting an operating power mode from the plurality of operating power modes;

(c) storing, responsive to a host processor, an indication of the selected operating power mode; and

(d) reducing power use of individual components of the storage device in accordance with the selected operating power mode, such that the storage device may still be read from and written to.

21. A method of managing power in a microprocessor controlled storage device as claimed in claim 20 in which the reducing step (d) comprises the steps of:

selecting a clock frequency for a microprocessor controlling the storage device; and

selecting a mode for accessing a memory array of the storage device during read and write operations.

22. A method of managing power in a microprocessor controlled storage device as claimed in claim 20 comprising a further step of initiating operation of the storage device in a lowest power mode.

23. A method of managing power in a microprocessor controlled storage device as claimed in claim 22 in which the reducing step (d) occurs only after a first operational command is provided to the storage device.