Multilayer amorphous silicon antifuse

• US 5,726,484 A
• Filed: 03/06/1996
• Issued: 03/10/1998
• Est. Priority Date: 03/06/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Hart, Michael J., Look, Kevin T., Karpovich, Yakov
• Primary Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/611,897
• Time in Patent Office: 734 Days
• Field of Search: 257/50, 257/52, 257/57, 257/530, 257/209, 438/600
• US Class Current: 257/530
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Claims

1. An antifuse comprising:

first and second conductive layers; and

an antifuse layer, positioned between the first and second conductive layers, having a thickness of less than about 100 nm, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm.

2. An antifuse according to claim 1 wherein the antifuse layer has a thickness of less than about 85 nm.

3. An antifuse according to claim 1 wherein the antifuse layer has a thickness of between about 20 and 85 nm.

4. An antifuse according to claim 1 wherein the oxide layer has opposing first and second surfaces, the first undoped amorphous silicon layer being in contact with the first surface and the second undoped amorphous silicon layer being in contact with the second surface.

5. An antifuse according to claim 1 wherein the oxide layer has a thickness of between about 1 and 10 nm.

6. An antifuse according to claim 1 wherein the oxide layer is grown from the amorphous silicon layer.

7. An antifuse according to claim 6 wherein the oxide layer is grown by a high dose Ar+ implant.

8. An antifuse according to claim 6 wherein the oxide layer is grown by an oxygen plasma.

9. An antifuse according to claim 6 wherein the oxide layer is formed by a self-limiting growth process.

10. An antifuse according to claim 1 wherein the amorphous silicon layer is formed in mole percentages of between about 8-12% H and between about 10-25% N.

11. An interconnect structure for interconnecting logic blocks in a programmable logic device comprising:

a plurality of antifuses, at least one antifuse including first and second conductive layers and an antifuse layer having a thickness of less than about 100 nm positioned between the first and second conductive layers, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm ; and

a plurality of interconnect lines, each line connected to at least one antifuse at either the first or second conductive layer of the antifuse.

12. An interconnect structure according to claim 11 wherein the antifuse layer has a thickness of less than about 85 nm.

13. An interconnect structure according to claim 11 wherein the antifuse layer has a thickness of between about 20 and 85 nm.

14. An interconnect structure according to claim 11 wherein the oxide layer has opposing first and second surfaces, the first undoped amorphous silicon layer being in contact with the first surface and the second undoped amorphous silicon layer being in contact with the second surface.

15. An interconnect structure according to claim 11 wherein the antifuse layer includes at least two oxide layers and at least three undoped amorphous silicon layers, each of the two oxide layers being positioned between a pair of undoped amorphous silicon layers.

16. An interconnect structure according to claim 11 wherein the oxide layer has a thickness of between about 1 and 10 nm.

17. An interconnect structure according to claim 11 wherein the plurality of antifuses are programmed by a range of programing voltages, the range forming a distribution having a standard deviation of less than about 0.30.

18. An interconnect structure according to claim 17 wherein the distribution of programing voltages has a standard deviation of less than about 0.20.

19. An interconnect structure according to claim 13 wherein the oxide layer is grown from the amorphous silicon layer.

20. An interconnect structure according to claim 19 wherein the oxide layer is formed by a self-limiting growth process.

21. A programmable logic device comprising:

a plurality of logic blocks;

an interconnect structure attached to each of the logic blocks for interconnecting two or more of the plurality of logic blocks, the interconnect structure including

a plurality of antifuses, at least one antifuse including first and second conductive layers and an antifuse layer having a thickness of less than about 100 nm positioned between the first and second conductive layers, the antifuse layer including first and second undoped amorphous silicon layers and an oxide layer positioned between the first and second undoped amorphous silicon layers, wherein the oxide layer has a thickness of less than about 10 nm, and

a plurality of interconnect lines, each line connected to at least one antifuse at either the first or second conductive layer of the antifuse.

22. A programmable logic device according to claim 21 wherein the antifuse layer has a thickness of less than about 85 nm.

23. A programable logic device according to claim 21 wherein the antifuse layer has a thickness of between about 20 and 85 nm.

24. A programmable logic device according to claim 21 wherein the oxide layer has opposing first and second surfaces, the first undoped amorphous silicon layer being in contact with the first surface and the second undoped amorphous silicon layer being in contact with the second surface.

25. A programmable logic device according to claim 21 wherein the antifuse layer includes at least two oxide layers and at least three undoped amorphous silicon layers, each of the two oxide layers being positioned between a pair of undoped amorphous silicon layers.

26. A programable logic device according to claim 21 wherein the oxide layer has a thickness of between about 1 and 10 nm.

27. A programable logic device according to claim 21 wherein the plurality of antifuses are programmed by a range of programing voltages, the range forming a distribution having a standard deviation of less than about 0.30.

28. A programable logic device according to claim 27 wherein the distribution of programing voltages has a standard deviation of less than about 0.20.

29. A programable logic device according to claim 21 wherein the oxide layer is grown from the amorphous silicon layer.

30. A programable logic device according to claim 29 wherein the oxide layer is formed by a self-limiting growth process.