Method and apparatus for independently resetting processors and cache controllers in multiple processor systems

  • US 5,737,604 A
  • Filed: 09/30/1996
  • Issued: 04/07/1998
  • Est. Priority Date: 11/03/1989
  • Status: Expired due to Term
First Claim
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1. A computer system responsive to a system reset signal and a processor only reset signal comprising:

  • a processor;

    system main memory for storing data and coded instructions;

    a system bus for transmitting program instructions, data and control signals;

    a hard disk memory coupled to said system main memory and said system bus;

    cache memory coupled to said processor and said system main memory for temporarily storing a duplication of a portion of the data and program instructions stored in said system main memory for high speed access by said processor;

    a cache memory controller connected to said processor, said cache memory, said system main memory and said system bus for determining whether program instructions or data required by said processor are resident in cache memory;

    cache reset circuitry coupled to said cache memory controller and receiving the system reset signal, said cache reset circuitry resetting said cache memory controller responsive to said system reset signal but unresponsive to said processor only reset signal; and

    processor reset circuity receiving the system reset signal and the processor-only reset signal, said processor reset circuit for resetting the processor responsive to said system reset signal or said processor-only reset signal.

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