Data transferring buffer
First Claim
1. Data transferring buffer circuits for data exchange, said data transferring buffer circuits receiving data from a plurality of data sources, providing the data to a plurality of data destinations and receiving a destination buffer limit signal from at least one of the plurality of data destinations, said data transferring buffer circuits comprising:
- a plurality of buffers connected to corresponding ones of the plurality of data sources to independently receive and store data in parallel the data sent from the plurality of data sources, each of said buffers providing a data remainder amount signal;
a buffer limit signal generating circuit, connected to said plurality of buffers, for generating a source buffer limit signal when an amount of data stored in one of said plurality of buffers reaches a predetermined limit and outputting the source buffer limit signal to one of a plurality of the data sources;
a data read signal generating circuit, connected to said plurality of buffers, for producing a selection signal to identify a selected buffer from among said plurality of buffers based on the data remainder amount signals from said plurality of buffers and the destination buffer limit signal from at least one of the plurality of data destinations indicating ability to receive the data from at least one of said buffers storing the data to be sent, and for supplying a data reading signal to the selected buffer; and
a selected data delivery circuit, connected to said data read signal generating circuit and said buffers, for receiving the selection signal from said data read signal generating circuit and for delivering the data, output by the selected buffer in response to the data reading signal, to each of the at least one of the plurality of data destinations capable of receiving the data as indicated by the destination buffer limit signal received therefrom.
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Abstract
Data transferring buffer circuits for data exchange include a plurality of buffers corresponding to a plurality of data sources for independently receiving and storing data sent from the plurality of data sources, and a buffer limit signal generating circuit for delivering a buffer limit signal when the amount of data stored in a buffer reaches a predetermined limit. The buffer circuits also include a data read signal generating circuit for selecting one of the buffers and generating a data reading signal for the selected buffer. The data reading signal is generated based on a remaining amount of data and information concerning a vacancy at a buffer to which data is to be supplied. The buffer circuits also include a selected data delivery circuit for adopting data selected by the data read signal generating circuit and for delivering the adopted data.
66 Citations
10 Claims
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1. Data transferring buffer circuits for data exchange, said data transferring buffer circuits receiving data from a plurality of data sources, providing the data to a plurality of data destinations and receiving a destination buffer limit signal from at least one of the plurality of data destinations, said data transferring buffer circuits comprising:
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a plurality of buffers connected to corresponding ones of the plurality of data sources to independently receive and store data in parallel the data sent from the plurality of data sources, each of said buffers providing a data remainder amount signal; a buffer limit signal generating circuit, connected to said plurality of buffers, for generating a source buffer limit signal when an amount of data stored in one of said plurality of buffers reaches a predetermined limit and outputting the source buffer limit signal to one of a plurality of the data sources; a data read signal generating circuit, connected to said plurality of buffers, for producing a selection signal to identify a selected buffer from among said plurality of buffers based on the data remainder amount signals from said plurality of buffers and the destination buffer limit signal from at least one of the plurality of data destinations indicating ability to receive the data from at least one of said buffers storing the data to be sent, and for supplying a data reading signal to the selected buffer; and a selected data delivery circuit, connected to said data read signal generating circuit and said buffers, for receiving the selection signal from said data read signal generating circuit and for delivering the data, output by the selected buffer in response to the data reading signal, to each of the at least one of the plurality of data destinations capable of receiving the data as indicated by the destination buffer limit signal received therefrom. - View Dependent Claims (2, 3)
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4. A system of data transfer between a plurality of processors in which data processing is carried out by exchanging data between each processor of the plurality of processors, said system comprising:
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groups of processors and switching modules arranged in a hierarchical structure including higher levels and lower levels producing data exchange request signals and sending and receiving data simultaneously and selectively, a first communication between a first processor belonging to a first group of processors and switching modules of the higher levels and a second processor belonging to a second group of processors and switching modules of the lower levels and a second communication between third and fourth processors, each belonging to the second group of processors and switching modules of the lower levels, being carried out independently of each other and simultaneously with each other; lower event transmission units, each having separate input and output connections directly to all of the processors in an associated lower level group of the processors and higher level input and output connections, to simultaneously receive the data exchange request signals from all of the processors in the associated lower level group and simultaneously output the data exchange request signals to at least one of the processors in the associated lower level group and the higher level output connection; and a first upper event transmission unit, connected to said lower event transmission units, for interconnecting said lower event transmission units, said first upper event transmission unit including; a data input circuit, connected to each of said lower event transmission units, for receiving the data from the processors belonging to the lower levels; a data holding circuit, connected to said data input circuit, for holding the received data from said data input circuit and providing the received data when a plurality of the data exchange request signals exist; and a selective data delivery circuit, connected to said data holding circuit, for receiving and selectively delivering the received data to one of the processors belonging to the lower levels via one of said lower event transmission units. - View Dependent Claims (5)
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6. Event transmission buffer circuits for selectively transferring data between data sources and data destinations, each of said event transmission buffer circuits comprising:
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internal buffer circuits provided for and connected to corresponding ones of the data sources, said internal buffer circuits receiving the data in parallel from the data sources, storing the data as stored data and generating a data remainder amount signal indicating an amount of stored data, each internal buffer circuit receiving, storing and generating independently of other internal buffer circuits; a buffer limit signal generating circuit, connected to said internal buffer circuits, for generating and providing buffer limit signals when an amount of the data stored in one of said internal buffer circuits reaches a predetermined limit; a data read signal generating circuit, connected to said internal buffer circuits, for selecting one of said internal buffer circuits in accordance with the data remainder amount signals from said internal buffer circuits and the buffer limit signals from another one of said event transmission buffer circuits, and for generating a data read signal for the one of said internal buffer circuits selected by said data read signal generating circuit; and a selected data delivery circuit, connected to said data read signal generating circuit, for receiving the stored data from the one of said internal buffer circuits and selectively providing the data, output by the one of said internal buffer circuits in response to the data read signal, to at least one of the data destinations. - View Dependent Claims (7)
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8. A data exchange unit for exchanging data among groups of processors, said data exchange unit provided for each group of processors, the groups of processors arranged in a lowest part of a hierarchical structure including upper data exchange units and lower data exchange units, and the processors generating data exchange request signals, said data exchange unit comprising:
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a data input circuit for simultaneously receiving data and a data exchange request signal from one to all of the processors of a same group and from one of the upper data exchange units, a first communication between a first processor belonging to the same group and a corresponding upper data exchange unit and a second communication between a second processor and a third processor, each belonging to the same group, are carried out independently of each other and simultaneously with each other; a data holding circuit, connected to said data input circuit, for receiving and holding the data from said data input circuit in accordance with the data exchange request signals; and a selective data delivery circuit, connected to said data holding circuit, for receiving the data held by said data holding circuit and selectively delivering the data to one or more of one of the processors belonging to the same group, one of the lower data exchange units, and one of the upper data exchange units.
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9. A data transfer buffer system for transferring data between data sources and data destinations, said data transfer buffer system including data exchange units, each of said data exchange units comprising:
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buffer circuits, respectively connected to each of the data sources, for independently receiving and storing data in parallel; remainder signal means for generating data remainder signals indicating stored amounts of data in each of said buffer circuits; limit signal means for generating buffer limit signals when at least one of said buffer circuits stores a predetermined amount of data; selecting means for receiving said buffer limit signals from another of said data exchange units corresponding to at least one of the data destinations, for generating a selection signal identifying a selected one of said buffer circuits and generating a read signal for the selected one of said buffer circuits dependent upon said data remainder signals from said remainder signal means and said buffer limit signals from the other of said data exchange units; and selective data output means for receiving the selection signal and for receiving and selectively providing the stored data, corresponding to the selected one of said buffer circuits, as output data for at least one of the data destinations.
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10. A system for data processing by hierarchically arranged processors exchanging data, said system comprising:
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processors, arranged in a hierarchical structure including at least one higher level and at least one lower level, to produce data exchange request signals, said processors in the at least one lower level formed in lower level groups with all lower level groups of said processors included in an upper level group of a next higher level; lower event transmission units, each having separate input and output connections directly to all of said processors in an associated lower level group of said processors and higher level input and output connections, to simultaneously receive the data exchange request signals from all of said processors in the associated lower level group and simultaneously output the data exchange request signals to at least one of said processors in the associated lower level group and the higher level output connection; and an upper event transmission unit to interconnect said lower event transmission units, said upper event transmission unit including a data input circuit, connected to the higher level output connection of each of said lower event transmission units, to receive the data exchange request signals from said lower level transmission units when the data exchange request signals are not directed from one of said processors to at least one other of said processors in a single lower level group; a data holding circuit, connected to said data input circuit, to hold a plurality of the data exchange request signals received by said data input circuit; and a selective data delivery circuit, connected to said data holding circuit and the higher level input connection of each of said lower event transmission units, to selectively deliver the data exchange request signals via said lower event transmission units to said processors in the at least one lower level.
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Specification