Input current shaping technique and low pin count for pfc-pwm boost converter

• US 5,742,151 A
• Filed: 06/20/1996
• Issued: 04/21/1998
• Est. Priority Date: 06/20/1996
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Micro Linear Corporation (Qorvo, Inc.)
• Inventors: Hwang, Jeffrey
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/670,181
• Time in Patent Office: 670 Days
• Field of Search: 323/222, 323/223, 323/207, 323/226, 323/273, 323/274, 323/282, 323/284, 363/20, 363/21, 363/89, 363/79, 363/80, 363/97, 363/101, 363/124, 363/131
• US Class Current: 323/222
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

An integrated circuit controller for power factor correction circuit that provides unity power factor by sensing only a current in the power factor correction circuit and a dc supply voltage. The power factor correction circuit is coupled to a circuit for generating the dc supply voltage. Thus, the dc supply voltage is representative of the regulated output voltage of the power factor correction circuit. The dc supply voltage is sensed and integrated over each clock cycle and compared to an inverted and amplified version of the sensed current for controlling operation of the power factor correction circuit. By sensing the dc supply voltage, rather than the output voltage of the power factor correction circuit, the integrated circuit requires fewer pins. In a preferred embodiment, the integrated circuit also includes a pulse width modulation controller circuit. Because a single clock signal is utilized for performing both leading edge modulation in the power factor correction circuit and trailing edge modulation in the pulse width modulation circuit, fewer pins are required. Therefore, the integrated circuit controls the power factor correction circuit and the pulse width modulation circuit while being contained within an eight-pin integrated circuit.

Claims

1. A power converter circuit comprising:

a. a switching mode power factor correction circuit comprising a first inductor and a second inductor inductively coupled to the first inductor wherein a first current in the first inductor charges an output capacitor and a second current in the second inductor is induced by the first current and provides power for generating a dc supply voltage; and

b. a control circuit for controlling switching of the power factor correction circuit for maintaining the first current in phase with an input voltage wherein the control circuit senses the dc supply voltage for controlling switching.

2. The circuit according to claim 1 wherein the control circuit is contained in an integrated circuit chip and wherein the dc supply voltage powers the integrated circuit chip.

3. The power converter circuit according to claim 1 wherein the control circuit includes means for controlling switching of a pulse width modulation circuit.

4. The power converter circuit according to claim 3 further comprising a pulse width modulation circuit coupled in cascade with the power factor correction circuit.

5. The power converter circuit according to claim 3 wherein the control circuit performs leading edge modulation for controlling switching of the power factor correction circuit and wherein the control circuit performs trailing edge modulation for controlling switching of the pulse width modulation circuit wherein the leading edge modulation and the trailing edge modulation are performed according to a single clock signal.

6. The power factor correction circuit according to claim 3 wherein the controller circuit is contained within an integrated circuit chip having eight or fewer pins.

7. A power converter circuit comprising:

a. an inductor coupled to receive a first current from a rectified supply;

b. a first switch coupled to control the first current for storing energy in the inductor;

c. a capacitor coupled to the inductor for receiving energy from the inductor for forming a first output voltage;

d. a control circuit including means for controlling the first switch;

e. means for forming a dc supply voltage for powering the control circuit wherein the dc supply voltage is representative of the first output voltage;

f. means for sensing the first current coupled to the means for controlling the first switch; and

g. means for sensing the dc supply voltage coupled to the means for controlling the first switch.

8. The power converter circuit according to claim 7 wherein the means for controlling the first switch comprises:

a. means for forming a voltage representative of the first current coupled to the means for sensing the first current;

b. means for integrating for forming an integrated signal by integrating over each of a series of clock cycles of a clock signal, a difference between a reference voltage and the dc supply voltage, the means for integrating coupled to the means for sensing the dc supply voltage;

c. means for comparing the voltage representative of the first current to the integrated signal for forming a first switch control signal wherein the means for comparing is coupled to the means for forming and to the means for integrating and wherein the first switch is controlled to open and to close based upon the first switch control signal and the clock signal.

9. The power converter circuit according to claim 8 further comprising a pulse width modulation stage coupled to receive the first output voltage for forming a second output voltage, the pulse width modulation stage comprising a second switch.

10. The power converter circuit according to claim 9 wherein the control circuit further comprises means for controlling the second switch, the means for controlling the second switch comprising:

a. means for sensing a second current in the pulse width modulation stage;

b. means for sensing the second output voltage; and

c. means for forming a second switch control signal for controlling the second switch wherein the means for forming is coupled to the means for sensing the second current and coupled to the means for sensing the second output voltage and wherein the second switch is controlled to open and to close based upon the second switch control signal and the clock signal.

11. The power converter circuit according to claim 10 wherein the means for controlling the first switch performs leading edge modulation and the wherein the means for controlling the second switch performs trailing edge modulation.

12. The power converter circuit according to claim 11 wherein the control circuit is contained in an integrated circuit wherein the integrated circuit requires not more than eight pins.

13. A power converter circuit comprising:

a. a rectifier having a positive output terminal and a negative output terminal;

b. a transformer having a primary winding and a secondary winding wherein a first terminal of the primary winding is coupled to the positive output terminal;

c. a diode having an anode and a cathode, wherein the anode is coupled to a second terminal of the primary winding;

d. a first switch having a first terminal and a second terminal wherein the first terminal of the first switch is coupled to the second terminal of the primary winding and wherein the second terminal of the first switch is coupled to a ground node;

e. a generating circuit for forming a dc supply voltage coupled to the secondary winding;

f. a capacitor having a first terminal and a second terminal wherein the first terminal of the capacitor is coupled to the cathode and the second terminal of the capacitor is coupled to the ground node;

g. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to the negative output terminal and the second terminal of the resistor is coupled to the ground node;

h. an amplifier having an input and an output wherein the input of the amplifier is coupled to the first terminal of the resistor;

i. a transconductor having a positive input, a negative input and an output wherein the positive input of the transconductor is coupled to receive a first reference voltage and the negative input of the transconductor is coupled to receive a voltage representative of the dc supply voltage;

j. an integrator having an input, an output and a reset terminal wherein the input of the integrator is coupled to the output of the transconductor;

k. a first comparator having a positive input, a negative input and an output wherein the positive input of the first comparator is coupled to the output of the integrator and the negative input of the first comparator is coupled to the output of the amplifier;

l. a second comparator having a positive input, a negative input and an output, wherein the positive input of the second comparator is coupled to receive a second reference voltage and the negative input of the second comparator is coupled to the first terminal of the resistor;

m. a first flip-flop having a set input, a reset input and an output wherein a reset input of the first flip-flop is coupled to the output of the first comparator;

n. a second flip-flop having a set input, a reset input and an output wherein a set input of the second flip-flop is coupled to the output of the second comparator;

o. an oscillator having an output for forming a clock signal wherein the output of the oscillator is coupled to the reset terminal of the integrator, to the set input of the first flip-flop and to the reset input of the second flip-flop; and

p. a logical NOR gate having a first input, a second input and an output wherein the output of the first flip-flop is coupled to the first input of the NOR gate and the output of the second flip-flop is coupled to the second input of the NOR gate and the output of the NOR gate is coupled to control a state of the first switch.

14. The power factor correction circuit according to claim 13 further comprising a load coupled across the capacitor.

15. The power factor correction circuit according to claim 14 wherein the load comprises a pulse width modulation circuit comprising a second switch.

16. The power factor correction circuit according to claim 15 wherein the amplifier, the transconductor, the integrator, the first comparator, the second comparator, the oscillator, the first flip-flop, the second flip-flop and the NOR gate are all contained within a single integrated circuit and wherein the single integrated circuit further comprises means for controlling the second switch.

17. The power factor correction circuit according to claim 16 wherein the means for controlling the first switch performs leading edge modulation and the wherein the means for controlling the second switch performs trailing edge modulation.

18. The power factor correction circuit according to claim 17 wherein the integrated circuit requires not more than eight pins.

19. A method of ensuring that an input current of a power converter follows an input voltage of the power converter in time and amplitude proportionately, the method comprising the steps of:

a. forming an input current in an inductor for storing energy in the inductor by closing a switch;

b. transferring energy from the inductor into a capacitor for forming an output voltage across the capacitor by opening the switch;

c. forming a voltage representative of the input current;

d. forming a dc supply voltage for an integrated circuit, wherein the dc supply voltage is representative of the output voltage; and

e. controlling opening and closing the switch according to the dc supply voltage and the voltage representative of the input current.

20. The method according to claim 19 wherein the step of controlling opening and closing the switch further comprises steps of:

a. sensing the dc supply voltage;

b. amplifying the voltage representative of the input current for forming an amplified first signal;

c. amplifying a difference between the dc supply voltage and a reference voltage for forming an amplified difference signal;

d. integrating the amplified difference signal over a each of a series of clock cycles of a clock signal for forming an integrated signal;

e. comparing the amplified difference signal to the integrated voltage for forming a switch control signal; and

f. controlling opening and closing the switch according to the switch control signal and the clock signal.

21. A method of ensuring that an input current of a power converter follows an input voltage of the power converter in time and amplitude proportionately, the method comprising the steps of:

a. forming an input current in an inductor for storing energy in the inductor by closing a switch;

b. transferring energy from the inductor into a capacitor for forming an output voltage across the capacitor by opening the switch;

c. forming a voltage representative of the input current;

d. inductively coupling a dc supply generating circuit to the inductor for forming a dc supply voltage; and

e. controlling opening and closing the switch according to the dc supply voltage and the voltage representative of the input current.

22. The method according to claim 21 wherein the step of controlling opening and closing the switch further comprises steps of:

a. sensing the dc supply voltage;

b. amplifying the voltage representative of the input current for forming an amplified first signal;

c. amplifying a difference between the dc supply voltage and a reference voltage for forming an amplified difference signal;

d. integrating the amplified difference signal over a each of a series of clock cycles of a clock signal for forming an integrated signal;

e. comparing the amplified difference signal to the integrated voltage for forming a switch control signal; and

f. controlling opening and closing the switch according to the switch control signal and the clock signal.