Capacitive pressure sensor and method of fabricating same

• US 5,744,725 A
• Filed: 01/08/1997
• Issued: 04/28/1998
• Est. Priority Date: 04/18/1994
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ross, Carl, Hughes, Donald L., Chen, Shiuh-Hui Steven
• Primary Examiner(s): Chilcot, Richard
• Assistant Examiner(s): MCCALL, ERIC SCOTT
• Application Number:
  US08/780,428
• Time in Patent Office: 475 Days
• Field of Search: 73/718, 73/721, 73/724, 361/283.1, 361/283.3, 361/283.4, 156/189
• US Class Current: 73/724
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

A capacitive pressure sensor and method of fabricating the sensor includes providing a layered structure including a second silicon layer (115), a second insulating layer (203, 205) in contact with the second silicon layer (115), a first silicon layer (123) in contact with the second insulating layer (203, 205), a first insulating layer (201) in contact with the first silicon layer (123), and a mask layer (221) in contact with the first insulating layer (201). A major exposed surface (220) of the second silicon layer (115) is provided by mechanically reducing a thickness (210) of the second silicon layer (115) to a predetermined thickness (116). Preferably this is done by grinding and then polishing the second silicon layer (115). In one embodiment a third insulating layer (211) is in contact with the second major surface (220) of the second silicon layer (115). A third silicon layer (101) having a fourth insulating layer (109) forming a perimeter structure (215) positioned above and surrounding a predefined area (114) of the third silicon layer (101). The perimeter structure (215) is bonded to the third insulating layer (211), wherein a chamber (113) is formed between the third insulating layer (211), the perimeter structure (215), and the predefined area (114). Preferably, a portion of the first silicon layer (123) is removed using an anisotropic etch step.

Claims

1. A method of fabricating a capacitive pressure sensor, the method comprising the steps of:

providing first and second silicon layers (123,

     115), wherein each of the first and second silicon layers (123,

     115) have an insulating layer (201, 203, 205,

     207) respectively in contact with a first major surface (202,

     204) and on a surface (206,

     208) opposing the first major surface (202,

     204);

mechanically reducing a thickness (210) of the second silicon layer (115) to a predetermined thickness (116) wherein the step of mechanically reducing exposes a second major surface (220) on the second silicon layer (115);

disposing a third insulating layer (211) onto the second major surface (220 of the second silicon layer (115);

providing a third silicon layer (101) having a fourth insulating layer (109) in contact with a portion (110) of a major surface (214) of the third silicon layer, wherein the fourth insulating layer (109) forms a perimeter structure (215) surrounding a predefined area (114) on the major surface (214) of the third silicon layer (101); and

bonding a top surface (270) of the perimeter structure (215) to the third insulating layer 211 oriented on the second silicon layer (115), wherein a chamber (113) is formed between the third insulating layer (211), the perimeter structure (215), and the predefined area (114).

2. A method in accordance with claim 1 further comprising a step of removing a portion of the first silicon layer (123), using an anisotropic etch step.

3. A method in accordance with claim 1 wherein the insulating layer (201, 203, 205, 207) respectively in contact with each of the first and second silicon layers (123, 115) has a thickness of less than five micrometers.

4. A method in accordance with claim 1 wherein the step of bonding a portion (240) of a fourth major surface (241) of the third insulating layer (211) to the perimeter structure (215) oriented on the third silicon layer (101) comprises fusing the third insulating layer to the perimeter structure (115) associated with the third silicon layer (101).

5. A method in accordance with claim 1 wherein the step of bonding a portion (240) of a fourth major surface (241) of the third insulating layer (211) to the perimeter structure (215) oriented on the third silicon layer (101) comprises electrostatically bonding the fourth major surface (240) of the third insulating layer (211), to the perimeter structure (115) associated with the third silicon layer (101).

6. A method in accordance with claim 1 wherein the step of forming a rigidizing structure by removing portions of the first silicon layer (123) comprises a step of removing portions of the first silicon layer (123) using an anisotropic etch step.

7. A method in accordance with claim 1 wherein the step of forming a rigidizing structure by removing portions of the mask layer (221) comprises a step of forming a rigidizing structure by removing portions of the mask layer (221) using a dry etch method.

8. A method in accordance with claim 7 wherein the step of forming a rigidizing structure by removing portions of the mask layer (221) using a dry etch method comprises a step of forming a rigidizing structure by removing portions of the mask layer (221) using a plasma etch method.

9. A method in accordance with claim 1 further comprising a step of metalizing selective surface areas of each of the second and third silicon layers (115, 101) to form conductive contact pads (129, 131).

10. A method in accordance with claim 1 wherein the step of providing a first silicon layer comprises providing a first silicon layer having a thickness more than twenty times thicker than the insulating layer provided in the step of providing first and second silicon layers (123, 115), having an insulating layer (201, 203, 205, 207) respectively in contact with a first major surface (202, 204) and on a surface (206, 208) opposing the first major surface (202, 204).

11. A method in accordance with claim 1 wherein the step of mechanically reducing comprises a step of grinding.

12. A method in accordance with claim 11 wherein the step of grinding includes a step of polishing.

13. A method of fabricating a capacitive pressure sensor, the method comprising the steps of:

providing first and second silicon layers (123,

     115), wherein each of the first and second silicon layers (123,

     115) have an insulating layer (201, 203, 205,

     207) respectively in contact with a first major surface (202,

     204) and on a surface (206,

     208) opposing the first major surface (202,

     204);

forming a bonded interface (209) positioned between the first and second silicon layers (123,

     115) by bonding together each of the insulating layers (203,

     205) oriented on each of the major surface'"'"'s (202,

     204) of each of the first and second silicon layers (123,

     115);

removing the insulating layer (207) oriented on the surface (208) opposing the first major surface (204) of the second silicon layer (115), and mechanically reducing the second silicon layer (115) to a predetermined thickness (116), wherein the step of removing and reducing exposes a second major surface (220) on the second silicon layer (115);

disposing an electrically insulating layer (211) on the second major surface (220) of the second silicon layer (115), wherein the second silicon layer (115) and the electrically insulating layer (211) form a diaphragm structure (298);

providing a third silicon layer (101) having first and second insulating layers (109,

     217) respectively in contact with a third major surface (214) and on a surface (216) opposing the third major surface (214);

removing a predefined volumetric area (114) of the insulating layer (109) oriented adjacent the third major surface (214) of the third silicon layer (101) leaving an exposed surface of uninsulated silicon (218) bounded within a perimeter structure (215) comprised of a portion of the insulating layer (109) surrounding the exposed surface of uninsulated silicon (218);

bonding a portion (240) of a fourth major surface (241) of the electrically insulating layer (211), indigenous to the diaphragm structure (298), to the perimeter structure (215) oriented on the third silicon layer (101), wherein the bonding step forms a cavity (113) encapsulated between an unbonded portion (242) of the fourth major surface (241) of the electrically insulating layer (211), the perimeter structure (215), and the exposed surface (218) of uninsulated silicon (218);

disposing a mask layer (221) onto a major surface (222) opposing the surface (206) that opposes the major surface (202) of the first silicon layer (123); and

forming a rigidizing structure by removing portions of the mask layer (221), the insulating layer (201) oriented on the surface (206) opposing the first major surface (202) of the first silicon layer (123), the insulating layer (203) oriented on the first major surface (202) of the first silicon layer (123), and the insulating layer (205) oriented of the first major surface (204) of the second silicon layer (115), wherein the step of removing exposes a major portion of the major surface (204) of the second silicon layer (115).

14. A method in accordance with claim 13 wherein the step of removing and reducing comprises a step of grinding.

15. A method in accordance with claim 13 wherein the insulating layer respectively in contact with each of the first and second silicon layers has a thickness of less than five micrometers.

16. A method in accordance with claim 13 wherein the step of bonding a portion of a fourth major surface of the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure oriented on the third silicon layer comprises fusing the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure associated with the third silicon layer.

17. A method in accordance with claim 13 wherein the step of bonding a portion of a fourth major surface of the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure oriented on the third silicon layer comprises electrostatically bonding the fourth major surface of the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure associated with the third silicon layer.

18. A method in accordance with claim 13 wherein the step of forming a rigidizing structure by removing portions of the first silicon layer comprises a step of removing portions of the first silicon layer using an anisotropic etch step.

19. A method in accordance with claim 13 wherein the step of forming a rigidizing structure by removing portions of the mask layer comprises a step of forming a rigidizing structure by removing portions of the mask layer using a dry etch method.

20. A method in accordance with claim 17 wherein the step of forming a rigidizing structure by removing portions of the mask layer using a dry etch method comprises a step of forming a rigidizing structure by removing portions of the mask layer using a plasma etch method.

21. A method in accordance with claim 13 further comprising a step of metalizing selective surface areas of each of the second and third silicon layers to form conductive contact pads.

22. A method in accordance with claim 13 wherein the step of providing a first silicon layer comprises providing a first silicon layer having a thickness more than twenty times thicker than the insulating layer provided in the step of providing first and second silicon layers, having an insulating layer disposed thereon.

23. A method of fabricating a capacitive pressure sensor, the method comprising the steps of:

providing first and second silicon layers, wherein each of the first and second silicon layers have an insulating layer respectively in contact with a first major surface and on a surface opposing the first major surface;

forming a bonded interface positioned between the first and second silicon layers by bonding together each of the insulating layers oriented on each of the major surface'"'"'s of each of the first and second silicon layers;

mechanically removing the insulating layer oriented on the surface opposing the first major surface of the second silicon layer, and reducing the second silicon layer to a predetermined thickness, wherein the step of mechanically removing and reducing exposes a second major surface on the second silicon layer;

disposing an electrically insulating layer on the second major surface of the second silicon layer, wherein the second silicon layer and the electrically insulating layer form a diaphragm structure;

providing a third silicon layer having first and second insulating layers respectively in contact with a third major surface and on a surface opposing the third major surface;

removing a predefined volumetric area of the insulating layer oriented adjacent the third major surface of the third silicon layer leaving an exposed surface of uninsulated silicon bounded within a perimeter structure comprised of a portion of the insulating layer surrounding the exposed surface of uninsulated silicon;

bonding a portion of a fourth major surface of the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure oriented on the third silicon layer, wherein the bonding step forms a cavity encapsulated between an unbonded portion of the fourth major surface of the electrically insulating layer, the perimeter structure, and the exposed surface of uninsulated silicon;

patterning a mask onto the insulating layer oriented on a surface opposing the bonded interface of the first silicon layer, wherein the mask is defined by a predetermined area;

removing a portion of the insulating layer associated with the surface opposing the bonded interface of the first silicon layer, the remaining insulating layer contained within an area of substantially the same dimension as the predetermined area of the mask provided in the step of patterning a mask;

removing a portion of the first silicon layer, leaving a remaining silicon structure bounded within substantially the same dimension as the predetermined area of the mask provided in the step of patterning a mask proximate the remaining insulating layer and a larger area adjacent the first major surface of the insulating layer; and

removing an additional portion of the insulating layers associated with the bonded interface positioned between the first and second silicon layers, wherein the remaining portion is substantially bounded within the larger area associated with the remaining silicon structure.

24. A method in accordance with claim 23 wherein the step of removing and reducing comprises a step of grinding and polishing.

25. A method in accordance with claim 24 wherein the insulating layer respectively in contact with each of the first and second silicon layers is an oxide layer having a thickness of less than five micrometers.

26. A method in accordance with claim 25 wherein the step of bonding a portion of a fourth major surface of the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure oriented on the third silicon layer comprises fusing the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure associated with the third silicon layer.

27. A method in accordance with claim 25 wherein the step of bonding a portion of a fourth major surface of the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure oriented on the third silicon layer comprises electrostatically bonding the fourth major surface of the electrically insulating layer, indigenous to the diaphragm structure, to the perimeter structure associated with the third silicon layer.

28. A method in accordance with claim 23 wherein the step of removing a portion of the first silicon layer (123) comprises a step of removing a portion of the first silicon layer (123) using an anisotropic etch step.

29. A method in accordance with claim 28 further comprising a step of metalizing selective areas of each of the exposed surfaces of each of the second and third silicon layers to form conductive contact pads.