Apparatus and method for securing captured data transmitted between two sources

• US 5,751,809 A
• Filed: 02/04/1997
• Issued: 05/12/1998
• Est. Priority Date: 09/29/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jones, Peter, Davis, Derek L.
• Primary Examiner(s): Cain, David C.
• Application Number:
  US08/795,452
• Time in Patent Office: 462 Days
• Field of Search: 380/10, 380/5, 380/20, 380/23, 380/49, 380/30, 348/207, 348/460, 348/552
• US Class Current: 713/176
• CPC Class Codes: H04L 2209/30 Compression, e.g. Merkle-Damgard construction
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/3236 using cryptographic hash functions
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/3263 involving certificates, e.g. public key certificate [PKC] or attribute certificate [AC]; Public key infrastructure [PKI] arrangements network architectures or network communication protocols for supporting authentication of entities using certificates in a packet data network H04L63/0823
• CPC Class Codes: H04L 9/50 using hash chains, e.g. blockchains or hash trees

Abstract

Implemented preferably within a video camera, a secure data capture device is used to prevent a captured data clip from be fraudulently altered without detection. The secure data capture device performs "time-bracketing" and/or "sequence ordering" operations to preserve data integrity through implementation of two registers incorporating a "State of the Universe" ("SOTU") number and a "sequence" number, respectively. Time-bracketing is performed by digitally signing a running hash value representing the data clip appended to the SOTU number before the digital signature is "timestamped". Sequence ordering is performed by digitally signing the digest of the data frame or multiple data frames along with the sequence number.

Claims

1. A semiconductor device comprising:

sensing means for capturing a data clip; and

cryptographic means, coupled to said sensing means, for preserving integrity of said data clip, said cryptographic means includes

storage means for storing a unique key pair, a running hash value and a State value,

processor means for performing operations on said data clip to establish that said data clip was captured after publication of said State value prior to said running hash value undergoing a time-stamping operation, and

bus means for enabling said processor means to communicate with said storage means, said bus means being coupled to said processor means and said storage means.

2. The semiconductor device according to claim 1, wherein said storage means of said cryptographic means further stores at least a sequence number being unique for each data frame of said data clip.

3. The semiconductor device according to claim 2, wherein said storage means of said cryptographic means includes a non-volatile memory element.

4. The semiconductor device according to claim 3, wherein said storage means of said cryptographic means further includes a volatile memory element.

5. The semiconductor device according to claim 4, wherein said storage means of said cryptographic means further includes a clip sequence storage element, said clip sequence storage element is non-volatile memory which contains a clip sequence number being a first plurality of bits of said sequence number.

6. The semiconductor device according to claim 5, wherein said storage means of said cryptographic means further includes a frame sequence storage element, said frame sequence storage element is volatile memory which contains a frame sequence number being a second plurality of bits of said sequence number.

7. The semiconductor device according to claim 6, wherein said storage means of said cryptographic means further includes a state storage element which contains said State value loaded prior to said sensing means capturing said data clip.

8. The semiconductor device according to claim 1, wherein said sensing means is a sensor including a pixel capture array and control logic controlling said pixel capture array.

9. The semiconductor device according to claim 1, wherein said processor means performing a hash operation on said data clip before subsequent storage in said storage means as a first portion of said running hash value.

10. The semiconductor device according to claim 9, wherein said processor means producing a hash result for each data frame of said data clip in which each hash result is subsequently stored in said storage means to collectively produce said first portion of said running hash value.

11. The semiconductor device according to claim 10, wherein said processor means concatenating said first portion of said running hash value with said State value to produce said running hash value, digitally signing said running hash value to be output to an external source performing the time-stamping operation.

12. The semiconductor device according to claim 11, wherein prior to said processing means concatenating said first portion of said running hash value with said State value, said processing means further concatenating at least one hash result with a corresponding sequence number to produce at least one serialized data frame forming said data clip.

13. The semiconductor device according to claim 1, wherein said cryptographic means further includes a random number generator to generate said unique key pair.

14. A semiconductor device comprising:

a sensor to capture a data clip; and

a cryptographic circuit coupled to said sensor, said cryptographic circuit being capable of preserving integrity of said data clip by establishing that said data clip was captured after publication of a State value, said cryptographic circuit includes

at least one storage element capable of containing said State value and a running hash value being a hash result of said data clip combined with said State value, said State value loaded prior to said sensor capturing said data clip,

a processor capable of (i) performing operations on said data clip to produce said hash result, (ii) digitally signing said running hash value and (iii) enabling at least said running hash value to be output for time-stamping, and

a bus coupled to said plurality of storage elements and to said processor, the bus enables said processor to communicate with said plurality of storage elements.

15. The semiconductor device according to claim 14, wherein said at least one storage element of said cryptographic circuit includes

a first storage element capable of containing a unique key pair;

a second storage element capable of containing said running hash value;

a third storage element capable of containing said State value loaded prior to said sensor capturing said data clip;

a fourth storage element capable of containing a clip sequence number which is incremented after power-up of the semiconductor device; and

a fifth storage element capable of containing a frame sequence number which is incremented after said sensor captures a data clip, said frame sequence number is appended to said clip sequence number to form a sequence number.

16. The semiconductor device according to claim 15, wherein at least said first storage element and said fourth storage element of said cryptographic circuitry are made of non-volatile memory.

17. The semiconductor device according to claim 16, wherein at least said fifth storage element of said cryptographic means is made of volatile memory.

18. The semiconductor device according to claim 14, wherein said cryptographic circuit further includes a random number generator to generate values associated with at least one key.

19. The semiconductor device according to claim 14, wherein said sensor includes a pixel capture array and control logic controlling said pixel capture array.

20. The semiconductor device according to claim 14, wherein prior to said processor of said cryptographic circuit producing said hash result, said processor concatenates at least one data frame with a corresponding sequence number to produce at least one serialized data frame forming said data clip.

21. A data capture system comprising:

a first source including;

a sensor to capture a data clip, and

a cryptographic circuitry coupled to said sensor, said cryptographic circuitry capable of performing a first time-bracketing procedure on said data clip to establish that said data clip was captured after publication of a State value, said cryptographic circuitry includes

at least one storage element to contain said State value,

a processor capable of producing a running hash value based on both a hash result of said data clip and said State value, and of digitally signing at least said running hash value, and

a bus coupled to said at least one storage element and to said processor, said bus enabling said processor to communicate with said at least one storage element; and

a second source in communication with the first source, the second source performing a second time-bracketing procedure by performing a time-stamping operation on information including said running hash value provided by the first source.

22. A data capture system comprising:

transmitting means for capturing a data clip and for preserving an integrity of said data clip by performing a first time bracketing procedure on said data clip before transmitting said data clip, said transmitting means includes

sensor means for capturing said data clip, and

cryptographic means, coupled to said sensing means, for preserving integrity of said data clip, said cryptographic means includes

storage means for storing a unique key pair, a running hash value and a State value,

processor means for performing operations on said data clip to establish that said data clip was captured after publication of said State value, and

bus means for coupling said processor means to said storage means; and

receiving means for receiving said running hash value from the transmitting means and for performing a second time-bracketing procedure by time-stamping information including said running hash value.

23. A method for preserving integrity of a data clip transmitted from a first source to a second source, the method comprising the steps of:

capturing a first data frame of the data clip;

producing a first serialized data frame by hashing at least said first data frame;

incorporating said first serialized data frame to a running hash value;

incorporating a State value to said running hash value;

digitally signing said running hash value to produce a digital signature of said running hash value; and

performing a time-stamping operation on at least said running hash value.

24. The method according to claim 23, wherein prior to said step of capturing said first data frame, the method further comprises a step of loading said State value into the first source.

25. The method according to claim 24, wherein prior to said step of capturing said first data frame, the method further comprises a step of loading a sequence number into the first source.

26. The method according to claim 25, wherein said step of loading said sequence number includes the steps of

loading a clip sequence number into a non-volatile memory element of the first source, said clip sequence number being a plurality of bits forming said sequence number;

and

loading a frame sequence number into a volatile memory storage element of the first source, said frame sequence number being a plurality of bits forming said sequence number, excluding said plurality of bits forming said clip sequence number.

27. The method according to claim 26, wherein said step of producing said first serialized data frame includes the step of

concatenating said first data frame with said sequence number associated with said first data frame to produce said first serialized data frame.

28. A semiconductor device comprising:

a sensor to capture a data clip; and

a cryptographic circuit coupled to the sensor, said cryptographic circuit including;

at least one storage element capable of containing a running hash value and a State value loaded prior to the data clip being captured,

a processor coupled to the at least one storage element, the processor capable of performing operations on the data clip to establish that the data clip was captured after publication of the State value prior to at least the running hash value being output from the cryptographic circuit.

29. The semiconductor device according to claim 28, wherein the processor executes a hash function on the data clip to produce a hash result being stored as a first portion of the running hash value.

30. The semiconductor device according to claim 28, wherein the processor produces a hash result for each data frame of the data chip to collectively produce a first portion of the running hash value.

31. The semiconductor device according to claim 30, wherein the processor combining the first portion of the running hash value with the State value to produce the running hash value and digitally signing said running hash value.

32. The semiconductor device according to claim 28 functioning as a microprocessor.

33. A capturing device comprising

an output port;

and

a semiconductor device capable of preserving integrity of a data clip before transmission to the output port, the semiconductor device including

a sensor to capture a data clip, and

a cryptographic circuit coupled to the sensor, said cryptographic circuit including

at least one storage element capable of storing a running hash value being a hash result of the data clip combined with a State value and the State value loaded prior to the data clip being captured, and

a processor coupled to the at least one storage element, the processor capable of performing operations on the data clip to establish that the data clip was captured after publication of the State value before the running hash value is output through the output port.

34. The capturing device according to claim 33, wherein the output port is coupled to a communication line to allow at least said running hash value to be downloaded to a computer system.

35. A cryptographic circuit comprising:

at least one storage element to contain a running hash value and a State value loaded prior to a data clip being captured; and

a processor coupled to the at least one storage element, the processor to perform operations on the data clip to establish that the data clip was captured after publication of the State value and prior to publication of information including at least the running hash value.

36. The cryptographic circuit according to claim 35, wherein the operations by the processor include performing a hash operation on the data clip before subsequent storage in the at least one storage element as a first portion of the running hash value.

37. The cryptographic circuit according to claim 35, wherein the operations by the processor include producing a hash result for at least one data frame of the data clip in which each hash result is subsequently stored in the at least one storage element to collectively produce the first portion of the running hash value.

38. The cryptographic circuit according to claim 37, wherein the operations by the processor include incorporating the State value with the first portion of the running hash value to produce the running hash value.

39. The cryptographic circuit according to claim 38, wherein the operations of the processor further include digitally signing the running hash value to be output to an external source performing a time-stamping operation.

40. The cryptographic circuit according to claim 38, wherein prior to the processor producing the running hash value, the processor further concatenating the hash result with a corresponding sequence number to produce at least one serialized data frame forming the data clip.

41. A method comprising the steps of:

capturing a first data frame;

producing a hash result of the first data frame;

producing a running hash value based on the hash result and a State value; and

performing a time-stamping operation on at least the running hash value.

42. The method according to claim 41, wherein prior to the computing step, the method further comprising the step of:

obtaining the State value from a remote source.

43. A semiconductor device comprising:

a sensor to capture a data clip; and

a cryptographic circuit coupled to the sensor, said cryptographic circuit including;

at least one storage element capable of containing a State value prior to the data clip being captured,

a processor coupled to the at least one storage element, the processor capable of producing a hash result for each data frame of the data clip to collectively produce a first portion of a running hash value and of performing operations on the data clip to establish that the data clip was captured after publication of the State value and prior to at least the running hash value being output from the cryptographic circuit.

44. The semiconductor device according to claim 43, wherein the processor capable of combining the first portion of the running hash value with the State value to produce the running hash value.

45. A capturing device comprising

an output port;

and

a device including

a sensor to capture a data clip, and

a cryptographic circuit coupled to the sensor, said cryptographic circuit including

at least one storage element capable of containing a State value loaded prior to the data clip being captured, and

a processor coupled to the at least one storage element, the processor capable of producing a hash result for each data frame of the data clip in order to produce a first portion of a running hash value and of performing operations on the data clip to establish that the data clip was captured after publication of the State value and before the running hash value is output through the output port.

46. The capturing device according to claim 45, wherein the output port is coupled to a communication line to allow at least said running hash value to be downloaded to a computer system.