Linearly regulated voltage multiplier

• US 5,754,417 A
• Filed: 10/29/1996
• Issued: 05/19/1998
• Est. Priority Date: 10/31/1995
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Nicollini, Germano
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Time in patent office: 567 Days
• Field of Search: 363/59, 363/60, 327/535, 327/536, 330/297, 330/96
• US Class Current: 363/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps for substrate bias voltage generators G05F3/205; for static stores G11C5/145, G11C16/06; charge pumping structures for internal polarisation H01L27/0222

Abstract

A regulating circuit for the output voltage of a voltage booster, of the type which comprises a first charge transfer capacitor adapted to draw electric charges from the supply terminal and transfer them to the output terminal, through electronic switches controlled by non-overlapped complementary phase signals, and a second charge storage capacitor connected between the output terminal and ground, further comprises an error amplifier which generates, during one of the operational phases, a DC voltage corresponding to the difference between a reference voltage and a divided voltage of the output voltage of the voltage booster; this DC voltage is applied directly to one end of the transfer capacitor.

Claims

1. A charge pump circuit having an input terminal for receiving a supply voltage and an output terminal for providing a boosted voltage with respect to the supply voltage, the charge pump circuit comprising:

a charge transfer capacitor having first and second terminals;

a first switch connected between the first terminal of the charge transfer capacitor and the input terminal;

a charge storage capacitor connected between the output terminal and a first voltage reference;

a second switch connected between the first terminal of the charge transfer capacitor and the output terminal;

a first resistor connected to the output terminal; and

an error amplifier including;

an operational amplifier having a first input terminal coupled to the output terminal of the charge pump circuit, a second input terminal coupled to a second voltage reference, and an output line connected solely to the second terminal of the charge transfer capacitor and not directly connected to any other components; and

a single feedback loop comprising the charge transfer capacitor, the second switch, and the first resistor connected between the first input terminal and the output line of the operational amplifier, the operational amplifier and the single feedback loop forming an integrator to integrate a difference between the second voltage reference and a voltage at the first input terminal of the operational amplifier based on the boosted voltage.

2. The circuit according to claim 1, further comprising:

a third switch positioned between the second input terminal of the operational amplifier and the first voltage reference for coupling the second input terminal of the operational amplifier to the first voltage reference; and

a fourth switch positioned between the second input terminal of the operational amplifier and the second voltage reference for coupling the second input terminal of the operational amplifier to the second voltage reference.

3. The circuit according to claim 2, further comprising a second resistor connected in series between the first resistor and the first voltage reference, the first and second resistors defining a voltage divider.

4. The circuit according to claim 3 wherein the first input terminal of the operational amplifier is an inverting input terminal and the second input terminal of the operational amplifier is a non-inverting input terminal.

5. The circuit according to claim 2 wherein the third and fourth switches are respectively controlled by third and fourth clock signals which are non-overlapped signals.

6. The circuit according to claim 5 wherein the first and second switches are respectively controlled by first and second clock signals in which the first clock signal is a voltage-boosted logic signal complementary to the third clock signal and the second clock signal is a voltage-boosted logic signal complementary to the fourth clock signal.

7. A charge pump circuit for use in an integrated semiconductor device, the charge pump circuit having an input terminal for receiving a supply voltage and an output terminal for providing a boosted voltage with respect to the supply voltage, the charge pump circuit comprising:

a charge transfer capacitor having first and second terminals;

a first switch connected between the first terminal of the charge transfer capacitor and the input terminal, the first switch being controlled by a first clock signal to couple the input terminal to the first terminal of the charge transfer capacitor in order to charge the charge transfer capacitor;

a charge storage capacitor connected between the output terminal and a first voltage reference;

a second switch connected between the first terminal of the charge transfer capacitor and the output terminal, the second switch being controlled by a second clock signal to couple the first terminal of the charge transfer capacitor to the output terminal in order to transfer the charge in the charge transfer capacitor to the charge storage capacitor;

a first resistor connected to the output terminal; and

an error amplifier including;

an operational amplifier having a first input terminal coupled to the output terminal of the charge pump circuit through the first resistor, a second input terminal coupled to a second voltage reference, and an output terminal connected to the second terminal of the charge transfer capacitor, wherein the charge transfer capacitor, the second switch, and the first resistor comprise a single integrating feedback loop connected between the first input terminal and the output terminal of the operational amplifier when the second switch couples the first terminal of the charge transfer capacitor to the output terminal wherein the single integrating feedback loop is the only feedback loop connected between the first input terminal and the output terminal of the operational amplifier.

8. The circuit according to claim 7, further comprising:

a third switch coupled between the second input terminal of the operational amplifier and the first voltage reference, the third switch being controlled by a third clock signal to couple the second input terminal of the operational amplifier to the first voltage reference; and

a fourth switch coupled between the second input terminal of the operational amplifier and the second voltage reference, the fourth switch being controlled by a fourth clock signal to couple the second input terminal of the operational amplifier to the second voltage reference.

9. The circuit according to claim 8, further comprising a second resistor connected in series between the first resistor and the first voltage reference, the first and second resistors defining a voltage divider.

10. The circuit according to claim 9 wherein the first input terminal of the operational amplifier is an inverting input terminal and the second input terminal of the operational amplifier is a non-inverting input terminal.

11. The circuit according to claim 8 wherein the third and fourth clock signals are non-overlapped phase logic signals.

12. The circuit according to claim 11 wherein the first clock signal is a voltage-boosted logic signal complementary to the third clock signal and the second clock signal is a voltage-boosted logic signal complementary to the fourth clock signal.

13. A voltage booster having an input terminal for receiving a supply voltage and an output terminal for supplying a boosted voltage with respect to the supply voltage, comprising:

a charge transfer capacitor;

a first switch controlled by a first drive signal to couple a first terminal of said charge transfer capacitor to the input terminal;

a second switch controlled by a second drive signal to couple the first terminal of said charge transfer capacitor to the output terminal;

a charge storage capacitor connected between the output terminal and a first voltage reference;

an error amplifier

comprising an operational amplifier having a first input terminal coupled to the output terminal, a second input terminal coupled to the first voltage reference through a third switch controlled by a third drive signal and coupled to a second voltage reference through a fourth switch controlled by a fourth drive signal, and an output terminal coupled to a second terminal of said charge transfer capacitor; and

a single integrating feedback loop comprising the charge transfer capacitor, the second switch, and the output terminal coupled between the first input terminal and the output terminal of the operational amplifier.

14. The voltage booster according to claim 13 wherein the first input terminal of the operational amplifier is an inverting input terminal and the second input terminal of the operational amplifier is a non-inverting input terminal.

15. The voltage booster according to claim 14 wherein the inverting input terminal of the operational amplifier is coupled to the output terminal through a voltage divider.

16. The voltage booster according to claim 15 wherein the voltage divider comprises a first resistor and a second resistor connected in series between the output terminal and the first voltage reference, a common terminal between the first and second resistors being connected to the inverting input terminal of the operational amplifier.

17. The voltage booster according to claim 16 wherein the charge transfer capacitor, the second switch, the output terminal, and the first resistor form the only integrating feedback loop for the operational amplifier connected between the output terminal and the inverting input terminal of the operational amplifier.

18. The voltage booster according to claim 17 wherein the third and fourth drive signals are non-overlapped phase logic signals.

19. The voltage booster according to claim 18 wherein the first drive signal is a voltage-boosted logic signal complementary of the third drive signal, and the second drive signal is a voltage-boosted logic signal complementary of the fourth drive signal.

20. The voltage booster according to claim 13 wherein the first and second switches are p-channel MOS transistors, and the third and fourth switches are n-channel MOS transistors.

21. The voltage booster according to claim 13 wherein the first voltage reference is a ground voltage reference.

22. A charge pump circuit having an input terminal coupled to receive a supply voltage and an output terminal for providing a boosted voltage with respect to the supply voltage, the charge pump circuit comprising:

an amplifier having a first input, a second input and an output line, the output line having only a single integrated component directly connected thereto;

a charge transfer capacitor having a first terminal coupled to the input terminal for receiving the supply voltage and a second terminal directly connected to the output line of the amplifier, the charge transfer capacitor being that single integrated component directly connected to the output line;

a charge storage capacitor connected to the output terminal for retaining the boosted voltage;

a first switch coupled between the first terminal of the charge transfer capacitor and the output terminal for coupling the first terminal of the charge transfer capacitor to the charge storage capacitor to provide the boosted voltage to the output terminal; and

an integrator comprising the amplifier having the first input coupled to the output terminal through a first resistor, the integrator integrating a difference between a voltage at the first input of the amplifier and a first reference voltage when the first switch is in a conducting state to generate an error signal at the output of the amplifier, the error signal being coupled to the second terminal of the charge transfer capacitor to regulate the boosted voltage, the charge transfer capacitor being the sole element directly connected to the amplifier output line.

23. The circuit according to claim 22 wherein the first switch, the charge transfer capacitor and the first resistor provide the sole feedback loop between the amplifier output line and the first input terminal of the amplifier.

24. The circuit according to claim 22 wherein the amplifier comprises an operational amplifier having an inverting input connected to the first resistor and a second resistor, a non-inverting input coupled to the first reference voltage through a second switch, and an output coupled to the second terminal of the charge transfer capacitor, the second resistor being connected between the first resistor and a ground voltage reference.

25. The circuit according to claim 22, further comprising:

a third switch coupled between the input terminal and the first terminal of the charge transfer capacitor; and

a fourth switch coupled between the non-inverting input of the operational amplifier and the ground voltage reference.

26. A method for providing a boosted voltage to an output terminal of a charge pump circuit coupled to receive a supply voltage, the method comprising:

coupling the supply voltage to a first plate of a charge transfer capacitor through a first switch by rendering the first switch conductive during a first period;

rendering the first switch non-conductive and coupling the first plate of the charge transfer capacitor to the output terminal and to a charge storage capacitor through a second switch by rendering the second switch conductive during a second period to provide the boosted voltage to the output terminal; and

generating an error signal by integrating a difference between a voltage based on the boosted voltage and a reference voltage through an amplifier and a single integrating feedback loop comprising the charge transfer capacitor, the second switch, and a voltage divider coupled to the output terminal; and

regulating the boosted voltage during the second period by applying the error signal to a second plate of the charge transfer capacitor from an output terminal of the amplifier.

27. The method according to claim 26 wherein the act of regulating the boosted voltage further comprises:

dividing the boosted voltage in the voltage divider to generate a divided voltage;

applying the divided voltage to an inverting input of the amplifier;

applying the reference voltage to a non-inverting input of the amplifier;

generating the error signal at an output of the amplifier by integrating a difference between the divided voltage and the reference voltage through the single integrating feedback loop.