Method and system for managing system bus communications in a data processing system

• US 5,754,804 A
• Filed: 01/30/1996
• Issued: 05/19/1998
• Est. Priority Date: 01/30/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheselka, Harry, Yarbrough, John Wagner, Mulkey, James Gregory, Lingafelt, Charles Steven, Hunter, Steven Wade
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US08/594,056
• Time in Patent Office: 840 Days
• Field of Search: 395/728, 395/730, 395/299, 395/305, 395/308, 395/200.03, 395/280, 395/284, 395/306
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

In a data processing system, a first system processor is coupled to a first system bus. The first system processor includes a first bus controller. A second system processor having a second bus controller is coupled to a second system bus. The first bus controller is then coupled to a management bus, and the second bus controller is coupled to the same management bus. Thereafter, at least one feature device is coupled to the first system bus, the second system bus, and the management bus. The feature device is also configured to communicate system processor communications with the first system processor via the first system bus. Next, a problem that affects system processor communications over the first system bus between the feature device and the first system processor is detected. In response to detecting such a communications problem, a command is sent to the feature device via the management bus. In response to receiving the command on the management bus, the feature device is configured to communicate system processor communications with the second system processor via the second system bus, wherein the feature device continues to operate in the data processing system as a result of communicating system processor communications with the second system processor via the second system bus in the presence of a problem that affects system processor communications over the first system bus. A second management bus may be coupled to the first bus controller, the second bus controller, and the feature device for providing a redundant management bus.

Claims

1. A method for increasing the performance and reliability of a data processing system, said method comprising the steps of:

coupling a first system processor to a first system bus, wherein said first system processor includes a first bus controller;

coupling a second system processor to a second system bus, wherein said second system processor includes a second bus controller;

coupling said first bus controller to a management bus;

coupling said second bus controller to said management bus;

coupling at least one feature device to said first system bus, said second system bus, and said management bus, wherein said at least one feature device is configured to communicate system processor communications with said first system processor via said first system bus;

detecting a problem that affects system processor communications over said first system bus between said at least one feature device and said first system processor;

sending a command on said management bus to said at least one feature device; and

in response to receiving said command from said management bus, configuring said at least one feature device to communicate system processor communications with said second system processor via said second system bus, wherein said data processing system including said at least one feature device continues to operate as a result of communicating system processor communications with said second system processor via said second system bus in the presence of a problem that affects system processor communications over said first system bus.

2. The method according to claim 1 further including:

coupling said first bus controller to a second management bus;

coupling said second bus controller to said second management bus; and

coupling said at least one feature device to said second management bus.

3. The method according to claim 2 further including the step of configuring said at least one feature device to communicate system processor communications with said second system processor via said second system bus in response to receiving said command via said second management bus.

4. The method according to claim 2 wherein the step of sending a command on said management bus to said at least one feature device includes the step of sending a command on said first and second management buses to said at least one feature device.

5. The method according to claim 1 wherein the step of detecting a problem that affects system processor communications over said first system bus between said at least one feature device and said first system processor includes detecting a problem in said first system processor that affects system processor communications over said first system bus between said at least one feature device and said first system processor.

6. The method according to claim 1 wherein data transferred via said first system bus includes parity data, and wherein the step of detecting a problem that affects system processor communications over said first system bus between said at least one feature device and said first system processor includes detecting a parity error in data on said first system bus.

7. A system for increasing the performance and reliability of a data processing system comprising:

means for coupling a first system processor to a first system bus, wherein said first system processor includes a first bus controller;

means for coupling a second system processor to a second system bus, wherein said second system processor includes a second bus controller;

means for coupling said first bus controller to a management bus;

means for coupling said second bus controller to said management bus;

means for coupling at least one feature device to said first system bus, said second system bus, and said management bus, wherein said at least one feature device is configured to communicate system processor communications with said first system processor via said first system bus;

means for detecting a problem that affects system processor communications over said first system bus between said at least one feature device and said first system processor;

means for sending a command on said management bus to said at least one feature device; and

means for configuring said at least one feature device to communicate system processor communications with said second system processor via said second system bus in response to receiving said command from said management bus, wherein said data processing system including said at least one feature device continues to operate as a result of communicating system processor communications with said second system processor via said second system bus in the presence of a problem that affects system processor communications over said first system bus.

8. The system according to claim 7 further including:

means for coupling said first bus controller to a second management bus;

means for coupling said second bus controller to said second management bus; and

means for coupling said at least one feature device to said second management bus.

9. The system according to claim 8 further including means for configuring said at least one feature device to communicate system processor communications with said second system processor via said second system bus in response to receiving said command via said second management bus.

10. The system according to claim 8 wherein said means for sending a command on said management bus to said at least one feature device includes means for sending a command on said first and second management buses to said at least one feature device.

11. The system according to claim 7 wherein said means for detecting a problem that affects system processor communications over said first system bus between said at least one feature device and said first system processor includes means for detecting a problem in said first system processor that affects system processor communications over said first system bus between said at least one feature device and said first system processor.

12. The system according to claim 7 wherein data transferred via said first system bus includes parity data, and wherein said means for detecting a problem that affects system processor communications over said first system bus between said at least one feature device and said first system processor includes means for detecting a parity error in data on said first system bus.

13. A backplane for increasing the performance and reliability of a data processing system comprising:

a first system bus adapted to couple to a first system processor and to at least one feature device, said first system bus for communicating system processor communications between said first system processor and said at least one feature device;

a second system bus adapted to couple to a second system processor and to said at least one feature device, said second system bus for communicating system processor communications between said second system processor and said at least one feature device; and

a management bus adapted to couple to a first system processor, a second system processor, and said at least one feature device.

14. The backplane according to claim 13 further including a second management bus adapted to couple to said first system processor, said second system processor, and said at least one feature device.

15. The backplane according to claim 13 wherein a number of conductors in said management bus is equal to two.

16. The backplane according to claim 13 wherein said first and second system buses include connectors adapted to couple to said first system processor or said second system processor, and to inhibit coupling to said at least one feature device.

17. The backplane according to claim 16 wherein said backplane includes a plurality of system processor slots and at least one feature device slot, wherein said plurality of system processor slots each include:

a management bus connector adapted to couple either said first system processor or said second system processor to said management bus; and

a system bus connector adapted to couple said first system processor to said first system bus or said second system processor to said second system bus, wherein said management bus connector is spaced apart from said system bus connector by a first distance;

and wherein said at least one feature device slot includes;

a management bus connector adapted to couple said at least one feature device to said management bus; and

first and second system bus connectors adapted to couple said at least one feature device to said first and second system buses, wherein said management bus connector is spaced apart from either of said first or second system bus connectors by a distance different from said first distance to inhibit connection of said first or second system processors in said at least one feature device slot and to inhibit connection of said at least one feature device in said plurality of system processor slots.

18. The backplane of claim 13, said backplane further including:

a plurality of system processor slots that are each adapted to couple either said first system processor or said second system processor to said management bus and at least one of said first system bus and said second system bus, each of said plurality of system processor slots coupling only a single one of said first system processor and said second system processor at a time; and

at least one feature device slot adapted to couple said at least one feature device to said management bus and to said first and second system buses.

19. The backplane of claim 13, wherein said management bus communicates control signals between first and said second system processors and said at least one feature device.

20. The backplane of claim 13, wherein:

said first system bus is further adapted to couple to said second system processor; and

said second system bus is further adapted to couple to said first system processor.