Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register

• US 5,758,195 A
• Filed: 06/07/1995
• Issued: 05/26/1998
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Balmer, Keith
• Primary Examiner(s): TOPLU, LUCIEN
• Application Number:
  US08/487,201
• Time in Patent Office: 1,084 Days
• Field of Search: 395/898, 395/562, 395/566, 395/567, 395/527, 395/568
• US Class Current: 712/300
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A data processing system including a data-memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than the first data size. The data processing system enables a data transfer by supplying an address to the data memory with zeros substituted for a predetermined number of least significant bits. The data processor receives a data word of the first data size corresponding to the altered address. The data processor stores data of a selected processor data size into a selected data register. If the processor data size is smaller than the first data size, then the date register stores a selected a subset of bits of the data word dependent upon the processor data size and the predetermined number of least significant address bits of said address. The selected processor data size is stored in a qualifier register which may be one of a plurality of qualifier registers corresponding to an address register used to generate the address. The data memory includes a plurality of write strobe inputs. The data processor repeats data recalled from a selected data registers of the selected processor data size a number of times to fill a data word of the first data size. The data processor enables selected write strobes dependent upon the processor data size and the predetermined number of least significant bits of the address.

Claims

1. A data processing system comprising:

a data memory having a data port for transferring data words having a first data size and an address port for receiving an address, said data memory storing data words having a second data size smaller than said first data size at a plurality of address locations;

a data processor including

a data port of said first data size connected to said data port of said data memory;

an address generator connected to said address port of said data memory for generating an address, said address generator supplying said generated address to said address port of said data memory, said address generator including

a plurality of address registers,

a plurality of index address registers,

a plurality of qualifier registers each corresponding to one and only one of said plurality of address registers, each of said plurality of qualifier registers storing an indication of a selected processor data size, said processor data size being no greater than said first data size and no less than said second data size,

an arithmetic unit having a first input connected to said plurality of address registers, a second input connected to said plurality of index address registers, said arithmetic unit forming an arithmetic combination of data stored in a selected one of said plurality of address registers and data stored in a selected one of said plurality of index registers as said address;

a plurality of data registers for storing data of a third data size larger than said second data size; and

a data alignor connected to said data port, said address generator and said plurality of data registers for receiving a data word of said first data size from said data memory via said data port and storing data of said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address into a selected one of said data registers, if said selected processor data size is smaller than said first data size said data alignor selecting a subset of bits of said data word of said first data size dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator and aligning said subset of bits of said data word of said selected processor data size into a set of least significant bits of said selected one of said plurality of data registers.

2. The data processing system of claim 1, wherein:

said first data size is an integral power of 2 multiple of said second data size; and

said first data size is an integral power of 2 multiple of each selected processor data size.

3. The data processing system of claim 1, wherein:

said address generator wherein

each of said plurality of qualifier registers stores an indication of either a zero extend mode or a sign extend mode; and

said data alignor

storing "0'"'"'s" in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said zero extend mode, and

storing bits corresponding to a most significant bit of said selected processor data size in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said sign extend mode.

4. The data processing system of claim 1, wherein:

said first data size is 32 bits;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.

5. The data processing system of claim 1, wherein:

said data memory includes write strobes for each addressable memory location of said second data size within data words of said first data size, said data memory enabled for writing data into corresponding individual addressable memory locations of said second data size within said data words of said first data size when active and disabled from writing data into corresponding individual addressable memory locations of said second data size within said data words of said first data size when inactive;

said data alignor repeats data recalled from a selected one of said plurality of data registers of said selected processor data size a number of times to fill said data port if said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address is less than said first data size, said data alignor enabling selected one or ones of said write strobes dependent upon said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address and said predetermined number of least significant bits of said address generated by said address generator.

6. The data processing system of claim 5, wherein:

said first data size is 32 bits;

said data memory has 4 write strobes;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.

7. The data processing system of claim 1, further comprising:

a data bus connected to said plurality of qualifier registers and said plurality of data registers for moving data from an instruction specified one of said plurality of data registers to an instruction specified one of said plurality of qualifier registers in response to a register move instruction specifying one of said plurality of plurality of data registers as a source and one of said plurality of qualifier registers as said destination.

8. The data processing system of claim 1, further comprising:

a data bus connected to said plurality of qualifier registers and said plurality of data registers for moving data from an instruction specified one of said plurality of qualifier registers to an instruction specified one of said plurality of data registers in response to a register move instruction specifying one of said plurality of qualifier registers as a source and one of said plurality of data registers as said destination.

9. The data processing system of claim 1, further comprising:

a stack pointer register storing an address of a data stack; and

a data bus connected to said plurality of qualifier registers and said data port for pushing data from an instruction specified one of said plurality of qualifier registers to said data port for storage at an addressable memory storage location corresponding to said address stored in said stack pointer in response to a register push instruction specifying one of said plurality of qualifier registers as a source.

10. The data processing system of claim 1, further comprising:

a stack pointer register storing an address of a data stack; and

a data bus connected to said plurality of qualifier registers and said data port for popping data via said data port from an addressable memory storage location corresponding to said address stored in said stack pointer to an instruction specified one of said plurality of qualifier registers in response to a register pop instruction specifying one of said plurality of qualifier registers as a destination.

11. A data processing system comprising

a data memory having a data port for transferring data words having a first data size and an address port for receiving an address, said data memory storing data words having a second data size smaller than said first data size at a plurality of address locations, said data memory including a plurality of write strobe inputs for each addressable memory location of said second data size within data words of said first data size, said data memory enabled for writing data into corresponding individual addressable memory locations of said second data size within said data words of said first data size when active and disabled from writing data into corresponding individual addressable memory locations of said second data size within data words of said first data size when inactive;

a data processor including

a data port of said first data size connected to said data port of said data memory;

an address generator connected to said address port of said data memory for generating an address, said address generator supplying said generated address to said address port of said data memory;

a plurality of data registers for storing data of a third data size larger than said second data size; and

a data alignor connected to said data port of said data processor, said address generator and said plurality of data registers, said data alignor repeating data recalled from a selected one of said plurality of data registers of a selected processor data size a number of times to fill said data port of said data processor if said selected processor data size is less than said first data size, said data alignor enabling selected one or ones of said write strobes dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator.

12. The data processing system of claim 11, wherein:

said data processor further includes a qualifier register storing an indication of said selected processor data size.

13. The data processing system of claim 11, wherein:

said address generator includes

a plurality of address registers;

a plurality of index address registers;

a plurality of qualifier registers each corresponding to one and only one of said plurality of address registers, each of said plurality of qualifier registers storing an indication of said selected processor data size;

an arithmetic unit having a first input connected to said plurality of address registers, a second input connected to said plurality of index address registers, said arithmetic unit forming an arithmetic combination of data stored in a selected one of said plurality of address registers and data stored in a selected one of said plurality of index registers as said address; and

said data alignor enabling selected one or ones of said-write strobes dependent upon said selected processor data size corresponding to said data size indicated by said qualifier register corresponding to said address register employed in calculation of a current address.

14. The data processing system of claim 13, further comprising:

a data bus connected to said plurality of qualifier registers and said plurality of data registers for moving data from an instruction specified one of said plurality of data registers to an instruction specified one of said plurality of qualifier registers in response to a register move instruction specifying one of said plurality of data registers as a source and one of said plurality of qualifier registers as said destination.

15. The data processing system of claim 13, further comprising:

a data bus connected to said plurality of qualifier registers and said plurality of data registers for moving data from an instruction specified one of said plurality of qualifier registers to an instruction specified one of said plurality of data registers in response to a register move instruction specifying one of said plurality of qualifier registers as a source and one of said plurality of data registers as said destination.

16. The data processing system of claim 13, further comprising:

a stack pointer register storing an address of a data stack; and

a data bus connected to said plurality of qualifier registers and said data port for pushing data from an instruction specified one of said plurality of qualifier registers to said data port for storage at an addressable memory storage location corresponding to said address store in said stack pointer in response to a register push instruction specifying one of said plurality of qualifier registers as a source.

17. The data processing system of claim 13, further comprising:

a stack pointer register storing an address of a data stack; and

a data bus connected to said plurality of qualifier registers and said data port for popping data via said data port from addressable memory storage location corresponding to said address stored in said stack pointer to one of said plurality of qualifier registers in response to a register pop instruction specifying one of said plurality of qualifier registers as a destination.

18. The data processing system of claim 11, wherein:

said first data size is 32 bits;

said data memory has 4 write strobes;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.

19. The data processing system of claim 11, wherein:

said first data size is an integral power of 2 multiple of said second data size; and

said first data size is an integral power of 2 multiple of each selected processor data size.

20. In a data processing system including a data memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than said first data size and a plurality of data registers, the method of data transfer comprising the steps of:

generating an address in the address generator employing a selected one of a plurality of address registers in calculation of said address;

storing an indication of a processor data size in each of a plurality of qualifier registers, said processor data size being no greater than said first data size and no less than said second data size, each qualifier register corresponding to one and only one of the address registers;

supplying said address generated by the address generator to the data memory;

receiving a data word of said first data size corresponding to said address; and

storing data of said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address into a selected one of said data registers, if said selected processor data size is smaller than said first data size selecting a subset of bits of said data word of said first data size dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator and aligning said subset of bits of said data word of said selected processor data size into a set of least significant bits of said selected one of said plurality of data registers.

21. The method of claim 20, further comprising:

storing an indication of either a zero extend mode or a sign extend mode in each of said plurality of qualifier registers;

wherein said step of storing data of said selected data size in said selected one of said data registers further includes

storing "0'"'"'s" in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said zero extend mode, and

storing bits corresponding to a most significant bit of said selected processor data size in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said sign extend mode.

22. The method of claim 20, wherein:

said first data size is 32 bits;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.

23. In a data processing system including a data memory storing data words having a first data size, said data memory including a plurality of write strobe inputs for each of a plurality of subsets of a second data size smaller than said first data size within data words of said first data size, said data memory enabled for writing data into corresponding individual addressable memory locations within said data words of said second data size when a corresponding write strobe is active and disabled from writing data into corresponding individual addressable memory locations when a corresponding write strobe is inactive, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than said first data size and a plurality of data registers, the method of data transfer comprising the steps of:

selecting a processor data size no larger than said first data size and no smaller than said second data size;

supplying an address generated by the address generator to the data memory;

repeating data recalled from a selected one of said plurality of data registers of said selected processor data size a number of times to fill a data word of said first data size if said selected processor data size is less than said first data size;

enabling selected one or ones of said write strobes dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator.

24. The method of claim 23, wherein:

said step of supplying said address generated by the address generator includes generating said address employing a selected one of a plurality of address registers in calculation of said address; and

said step of selecting a processor data size includes storing an indication of a processor data size in each of a plurality of qualifier registers, each qualifier register corresponding to one and only one of the address registers and selecting said indication of said processor data size stored in said qualifier register corresponding to said address register employed in calculation of a current address.

25. The method of claim 23, wherein:

said first data size is 32 bits;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.

26. A data processing system comprising:

a data memory having a data port for transferring data words having a first data size and an address port for receiving an address, said data memory storing data words having a second data size smaller than said first data size at a plurality of address locations;

a data processor including

a data port of said first data size connected to said data port of said data memory;

an address generator connected to said address port of said data memory for generating an address, said address generator supplying said generated address to said address port of said data memory, said address generator including

a plurality of address registers,

a plurality of index address registers,

a plurality of qualifier registers each corresponding to one and only one of said plurality of address registers, each of said plurality of qualifier registers storing an indication of either a zero extend mode or a sign extend mode,

an arithmetic unit having a first input connected to said plurality of address registers, a second input connected to said plurality of index address registers, said arithmetic unit forming an arithmetic combination of data stored in a selected one of said plurality of address registers and data stored in a selected one of said plurality of index registers as said address;

a plurality of data registers for storing data of said third data size; and

a data alignor connected to said data port, said address generator and said plurality of data registers for receiving a data word of said first data size from said data memory via said data port and storing data of a selected processor data size not greater than said first data size and not less than said second data size into a selected one of said data registers, if said selected processor data size is smaller than said first data size said data alignor

selecting a subset of bits of said data word of said first data size dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator,

aligning said subset of bits of said data word of said selected processor data size into a set of least significant bits of said selected one of said plurality of data registers,

storing "0'"'"'s" in most significant bits of said selected one of said plurality of data registers if said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said zero extend mode, and

storing bits corresponding to a most significant bit of said selected processor data size in most significant bits of said selected one of said plurality of data registers if said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said sign extend mode.

27. The data processing system of claim 26, wherein:

said first data size is an integral power of 2 multiple of said second data size; and

said first data size is an integral power of 2 multiple of each selected processor data size.

28. The data processing system of claim 26, wherein:

said first data size is 32 bits;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.

29. The data processing system of claim 26, wherein:

said data memory includes write strobes for each addressable memory location of said second data size within data words of said first data size, said data memory enabled for writing data into corresponding Individual addressable memory locations of said second data size within said data words of said first data size when active and disabled from writing data into corresponding individual addressable memory locations of said second data size within said data words of said first data size when inactive;

said data alignor repeats data recalled from a selected one of said plurality of data registers of said selected processor data size a number of times to fill said data port if said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address is less than said first data size, said data alignor enabling selected one or ones of said write strobes dependent upon said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address and said predetermined number of least significant bits of said address generated by said address generator.

30. The data processing system of claim 26, wherein:

said first data size is 32 bits;

said data memory has 4 write strobes;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.

31. The data processing system of claim 26, further comprising:

a data bus connected to said plurality of qualifier registers and said plurality of data registers for moving data from an instruction specified one of said plurality of data registers to an instruction specified one of said plurality of qualifier registers in response to a register move instruction specifying one of said plurality of data registers as a source and one of said plurality of qualifier registers as said destination.

32. The data processing system of claim 26, further comprising:

a data bus connected to said plurality of qualifier registers and said plurality of data registers for moving data from an instruction specified one of said plurality of qualifier registers to an instruction specified one of said plurality of data registers in response to a register move instruction specifying one of said plurality of qualifier registers as a source and one of said plurality of data registers as said destination.

33. The data processing system of claim 26, further comprising:

a stack pointer register storing an address of a data stack; and

a data bus connected to said plurality of qualifier registers and said data port for pushing data from an instruction specified one of said plurality of qualifier registers to said data port for storage at an addressable memory storage location corresponding to said address stored in said stack pointer in response to a register push instruction specifying one of said plurality of qualifier registers as a source.

34. The data processing system of claim 26, further comprising:

a stack pointer register storing an address of a data stack; and

a data bus connected to said plurality of qualifier registers and said data port for popping data via said data port from an addressable memory storage location corresponding to said address store in said stack pointer to an instruction specified one of said plurality of qualifier registers in response to a register pop instruction specifying one of said plurality of qualifier registers as a destination.

35. In a data processing system including a data memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than said first data size and a plurality of data registers, the method of data transfer comprising the steps of:

generating an address in the address generator employing a selected one of a plurality of address registers in calculation of said address;

storing an indication either a zero extend mode or a sign extend mode of in each of a plurality of qualifier registers, each qualifier register corresponding to one and only one of the address registers;

supplying said address generated by the address generator to the data memory;

receiving a data word of said first data size corresponding to said address;

storing data of said selected processor data size of said stored indication of said qualifier register corresponding to said address register selected in calculation of a current address into a selected one of said data registers, if said selected processor data size is smaller than said first data size selecting a subset of bits of said data word of said first data size dependent upon said selected processor data size and a predetermined number of least significant bits of said address generated by said address generator;

aligning said subset of bits of said data word of said selected processor data size into a set of least significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size;

storing "0'"'"'s" in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said zero extend mode; and

storing bits corresponding to a most significant bit of said selected processor data size in most significant bits of said selected one of said plurality of data registers if said selected processor data size is smaller than said first data size and said qualifier register corresponding to said address register employed in calculation of a current address stores an indication of said sign extend mode.

36. The method of claim 35, wherein:

said first data size is 32 bits;

said data memory has 4 write strobes;

each of said plurality of data registers stores 32 bits;

said second data size is 8 bits; and

said selected processor data size is either 8 bits, 16 bits or 32 bits.