Charge storage for sensing operations in a DRAM

  • US 5,761,112 A
  • Filed: 09/20/1996
  • Issued: 06/02/1998
  • Est. Priority Date: 09/20/1996
  • Status: Expired due to Term
First Claim
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1. An integrated dynamic random access memory comprising:

  • an array of memory cells;

    a plurality of bit lines, wherein each bit line couples to memory cells in a column associated with the bit line;

    a plurality of sense amplifiers coupled to the bit lines;

    a power line coupled to provide power to the sense amplifiers;

    one or more on-chip capacitors which are coupled to the power line; and

    a transistor coupled between the sense amplifiers and the on-chip capacitors.

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