Identifiable modules on a serial bus system and corresponding identification methods

• US 5,761,697 A
• Filed: 11/02/1994
• Issued: 06/02/1998
• Est. Priority Date: 11/19/1990
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Lee, Robert D., Kurkowski, Hal, Curry, Stephen M., Bolan, Michael L., Dias, Donald R.
• Primary Examiner(s): Moore, David M.
• Assistant Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US08/333,571
• Time in Patent Office: 1,308 Days
• Field of Search: 395/427, 395/490, 395/474, 395/477, 395/481, 395/478, 395/404, 395/401, 395/281, 395/284, 395/287, 395/293, 395/290, 395/306, 340/870.14
• US Class Current: 711/100
• CPC Class Codes: G01K 1/028 arrangements for numerical indication
• CPC Class Codes: G01K 3/10 in respect of time, e.g. reacting only to a quick change of temperature
• CPC Class Codes: G01K 7/245 in an oscillator circuit
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: G06F 3/04897 Special input arrangements or commands for improving display capability
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 7/0021 for reading/sensing record carriers having surface contacts
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A single wire data bus is utilized by a bus master to communicate with and identify electronic devices also connected to the single wire data bus. Each of the electronic devices include a unique ID (identification), wherein the bus master, using a one-wire protocol, can identify all of the electronic devices connected to the single wire data bus.

Claims

1. A system with identifiable electronic devices on a single wire data bus, comprising;

(a) a bus master;

(b) said single wire data bus electrically coupled to said bus master;

(c) a plurality of electronic devices, each electronic device of said plurality of electronic devices electrically coupled to said single wire data bus, and each electronic device of said plurality of electronic devices having a unique n-bit identification; and

(d) each electronic device of said plurality of electronic devices having control logic programmable to respond to a signal sequence of first read signal, second read signal, write signal, said write signal comprised of a write bit, on said single wire data bus from said bus master by

(i) responding to said first read signal by signaling to said single wire data bus a jth bit of said unique n-bit identification, wherein j is positioned between 0 and n, said jth bit having a complement value,

(ii) responding to said second read signal by signaling to said single wire data bus the complement of said jth bit, and

(iii) responding to said write signal by comparing said write bit to said jth bit and

(A) when said write bit differs from said jth bit in one electronic device in said plurality of electronic devices, then idling said one electronic device in said plurality of electronic devices or

(B) when said write bit matches said jth bit, then incrementing to the (j+1)st bit of said unique n-bit identification if j is less than n.

2. The system with identifiable electronic devices on a single wire data bus of claim 7, wherein:

(a) said unique n-bit identification has 64 bits; and

(b) after 64 iterations of the signal sequence of first read signal, second read signal, and write signal of step (d) of claim 7 yields 64 consecutive matches of said write bit to a corresponding bit of said unique n-bit identification of a first electronic device of said plurality of electronic devices, said bus master can program a command into said control logic of said first electronic device of said plurality of electronic devices.

3. The system with identifiable electronic devices on a single wire data bus of claim 1, wherein:

(a) each electronic device of said plurality of electronic devices having said control logic programmable to respond to a write signal on said single wire data bus from said bus master by comparing said write bit to said jth bit and (A) when said write bit differs from said jth bit in one electronic device in said plurality of electronic devices, then idling said one electronic device in said plurality of electronic devices or (B) when said write bit matches said jth bit, then incrementing to said (j+1)st bit of said unique n-bit identification of said one electronic device in said plurality of electronic devices if j is less than n.

4. The system with identifiable electronic devices on a single wire data bus of claim 3, wherein:

(a) said unique n-bit identification has 64 bits; and

(b) after 64 iterations of said write signal of step (a) of claim 3 yields 64 consecutive matches of said write bit to a corresponding said unique n-bit identification of a first electronic device, said bus master can program a command into said control logic of said first electronic device.

5. The system with identifiable electronic devices on a single wire data bus of claim 1, wherein:

(a) each electronic device of said plurality of electronic devices having said control logic programmable to respond to a read signal on said single wire data bus from said bus master by signaling said jth bit of said unique n-bit identification and then incrementing to said (j+1)st bit of said unique n-bit identification if j is less than n.

6. The system with identifiable electronic devices on a single wire data bus of claim 5, wherein

(a) said unique n-bit identification has 64 bits;

and

(b) after 64 iterations of said read signal of step (a) of claim 5, said bus master can program a command into said control logic of said first electronic device.

7. The system with identifiable electronic devices on a single wire data bus of claim 1, wherein each electronic device of said plurality of electronic devices is mountable to a physical item.

8. The system with identifiable electronic devices ion a single wire data bus of claim 7, wherein each electronic device of said plurality of electronic devices is mountable to said physical item, further wherein said physical item is selected from the group consisting of maintenance records, retail products, machinery, cards, personnel identification badges, and/or any combination thereof.

9. The system with identifiable electronic devices on a single wire data bus of claim 1, wherein said identifiable electronic devices are integrated circuits.

10. The system with identifiable electronic devices on a single wire data bus of claim 1 wherein said single wire data bus is comprised of a single conductive path.

11. A system with identifiable electronic devices on a single wire data bus, comprising:

(a) a bus master;

(b) said single wire data bus electrically coupled to a bus master;

(c) a plurality of electronic devices, each electronic device of said plurality of electronic devices electrically coupled to said single wire data bus, and each electronic device of said plurality of electronic devices having a unique n-bit identification number;

(d) each electronic device of said plurality of electronic devices having electronic device control logic programmable to respond to a reset signal issued by said master by issuing a presence signal;

said bus master has master control logic configured to read from a first bit from said single wire data bus;

(i) said electronic device control logic of each electronic device of said plurality of electronic devices configured to respond by placing said first bit of said unique n-bit identification number of each electronic device of said plurality of electronic devices on said single wire data bus, which are logically combined with one another to produce a first logical combination,

(ii) said bus master control logic configured to read said first logical combination of said unique n-bit identification number of each electronic device of said plurality of electronic devices on said single wire data bus,

(iii) said electronic device control logic of each electronic device of said plurality of electronic devices configured to respond by placing a complement of said first bit of said unique n-bit identification number of each electronic device of said plurality of electronic devices on said single wire data bus which are logically combined to produce a second logical combination,

(iv) said bus master control logic reads said second logical combination and interprets said first logical combination in conjunction with said second logical combination to determine a portion of said unique n-bit identification number of at least one electronic device of said plurality of electronic devices, so that said master control logic can deselect at least one electronic device of said plurality of electronic devices.

12. The system of claim 11, further wherein each electronic device of said plurality of electronic devices is comprised of memory having data stored therein and said bus master reads said data from said memory of a selected electronic device after said selected electronic device has been identified.

13. The system of claim 11, wherein said n equals 64.

14. The system of claim wherein said first logical combination and said second logical combination are an AND operation.

15. A method of identifying a first electronic device in a plurality of electronic devices electrically coupled to a single wire data bus, each electronic device of said plurality of electronic devices having a unique n-bit identification number, comprising

(a) initiating a signal sequence of first read signal, second read signal, write signal, said write signal comprised of a write bit, on said single wire data bus to be received by each electronic device of said plurality of electronic devices;

(b) responding to said signal sequence of said first read signal, said second read signal, said write signal on said single wire data bus from said bus master by

(i) responding to said first read signal by signaling to said single wire data bus a jth bit of said unique n-bit identification number, wherein j is positioned between 0 and n,

(ii) responding to said second read signal by signaling to said single wire data bus a complement of said jth bit, and

(iii) responding to said write signal by comparing said write bit to said jth bit and

(A) when said write bit differs from said jth bit of one electronic device of said plurality of electronic devices, then idling said one electronic device of said plurality of electronic devices or

(B) when said write bit matches said jth bit, then incrementing to the (j+1)st bit of said unique n-bit identification number if j is less than n.

16. The method of identifying a first electronic device in a plurality of electronic devices electrically coupled to a single wire data bus of claim 15, wherein

(a) said unique n-bit identification number has 64 bits and said first electronic device having control logic;

and

(b) programming a command into control logic of said first electronic device when 64 iterations of said signal sequence of first read signal, second read signal, and write signal of step (d) of claim 15 yields 64 consecutive matches of said write bit to a corresponding bit of said unique n-bit identification number of said first electronic device.

17. The method of identifying a first electronic device in a plurality of electronic devices electrically coupled to a single wire data bus of claim 15, further comprising the steps of comparing said write bit to said jth bit and (A) when said at least one write bit differs from said jth bit of a first electronic device of said plurality of electronic devices, then idling said first electronic device of said plurality of electronic devices or (B) when said write bit matches said jth bit, then incrementing to said (j+1)st bit of said unique n-bit identification number if j is less than n.

18. The method of identifying a first electronic device in a plurality of electronic devices electrically coupled to a single wire data bus of claim 17, wherein:

(a) said unique n-bit identification number has 64 bits; and

(b) after 64 iterations of the write signal of step (A) of claim 17 yields 64 consecutive matches of said write bit to a corresponding bit of said unique n-bit identification number of a first electronic device, said bus master can program a command into control logic of said first electronic device.

19. The method of identifying a first electronic device in a plurality of electronic devices electrically coupled to a single wire data bus of claim 15, wherein

(a) programming control logic in a first electronic device of said plurality of electronic devices in response to a signal read on said single wire data bus from said bus master by signaling said jth bit of said unique n-bit identification number of said first electronic device of said plurality of electronic devices and then incrementing to said (j+1)st bit of said unique n-bit identification number of said first electronic device of said plurality of electronic devices if j is less than n.

20. The method if identifying a first electronic device in a plurality of electronic devices electrically coupled to a single wire data bus of claim 19, wherein:

(a) said unique n-bit identification number has 64 bits; and

(b) programming a command into said control logic of said first electronic device when 64 iterations of said read signal or step (a) of claim 19 of said bus master.