Electrically alterable non-volatile memory with N-bits per cell

• US 5,764,571 A
• Filed: 02/27/1995
• Issued: 06/09/1998
• Est. Priority Date: 02/08/1991
• Status: Expired due to Term

• Current Assignee: MLC Intellectual Property, LLC
• Original Assignee: BTG USA, Inc.
• Inventors: Banks, Gerald J.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/410,200
• Time in Patent Office: 1,198 Days
• Field of Search: 365/189.01, 365/189.07, 365/168, 365/201
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An electrically alterable, non-volatile multi-bit memory cell has Kⁿ predetermined memory states (Kⁿ >2), where K is a base of a predetermined number system and n is a number of bits stored per cell. Programming of the cell is verified by selecting a reference signal corresponding to the information to be stored and comparing a signal of the cell with the selected reference signal.

Claims

1. A multi-level memory device comprising:

an electrically alterable non-volatile multi-level memory cell for storing input information in a corresponding one of Kⁿ predetermined memory states of said multi-level memory cell, where K is a base of a predetermined number system, n is a number of bits stored per cell, and Kⁿ >

2;

memory cell programming means for programming said multi-level memory cell in accordance with said input information;

reference voltage selecting means for selecting one of a plurality of reference voltages in accordance with said input information, each of said reference voltages corresponding to a different one of said predetermined memory states; and

comparator means for comparing a voltage of said multi-level memory cell with the selected reference voltage, said comparator means further generating a control signal indicating whether the state of said multi-level memory cell is the state corresponding to said input information.

2. A device according to claim 1, wherein each memory state is bounded by one or more voltage values, and each reference voltage differs from the voltage value or values bounding the corresponding memory state.

3. Multi-level memory apparatus, comprising

an electrically alterable non-volatile memory cell having more than two predetermined memory states;

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell; and

a comparator which compares a signal corresponding to the state of said memory cell with the selected reference signal to verify whether said memory cell is programmed to the state indicated by said information.

4. Apparatus according to claim 3, wherein said comparator compares a bit line signal of said memory cell with the selected reference signal.

5. Apparatus according to claim 3, wherein said comparator compares a bit line voltage of said memory cell with a voltage of the selected reference signal.

6. Multi-level memory apparatus, comprising:

an electrically alterable non-volatile memory cell having more than two predetermined memory states;

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell; and

a verifying device which detects a parameter indicating the state of said memory cell and verifies whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal.

7. Apparatus according to claim 6, wherein said verifying device detects said parameter at a bit line terminal of said memory cell.

8. Apparatus according to claim 6, wherein said parameter is a bit line voltage of said memory cell.

9. Multi-level memory apparatus, comprising:

an electrically alterable non-volatile memory cell having more than two predetermined memory states;

a selecting device which selects one of a plurality of predetermined reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

a programming signal source which applies a programming signal to said memory cell; and

a comparator which compares a signal corresponding to the state of said memory cell with the selected reference signal to verify whether said memory cell is programmed to the state indicated by said information.

10. Apparatus according to claim 9, wherein said comparator compares a bit line signal of said memory cell with the selected reference signal.

11. Apparatus according to claim 9, wherein said comparator compares a bit line voltage of said memory cell with a voltage of the selected reference signal.

12. Multi-level memory apparatus, comprising:

an electrically alterable non-volatile memory cell having more than two predetermined memory states;

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

a programming signal source which applies a programming signal to said memory cell; and

a verifying device which detects a parameter indicating the state of said memory cell and which verifies whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal.

13. Apparatus according to claim 12, wherein said verifying device detects said parameter at a bit line terminal of said memory cell.

14. Apparatus according to claim 12, wherein said parameter is a bit line voltage of said memory cell.

15. Multi-level memory apparatus, comprising:

an electrically alterable non-volatile memory cell having more than two predetermined memory states;

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

a programming signal source which applies a programming signal to said memory cell; and

a control device which controls the application of said programming signal to said memory cell based on the selected reference signal.

16. Apparatus according to claim 15, wherein said control device detects a parameter indicating the state of said memory cell, verifies whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal, and controls the application of said programming signal to said memory cell based on a result of the verification.

17. Apparatus according to claim 15, wherein said control device compares a signal corresponding to the state of said memory cell with the selected reference signal and controls the application of said programming signal to said memory cell based on a result of the comparison.

18. Apparatus for verifying programming of an electrically alterable non-volatile memory cell having more than two predetermined memory states, comprising:

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell; and

a comparator to compare a signal corresponding to the state of said memory cell with the selected reference signal to verify whether said memory cell is programmed to the state indicated by said information.

19. Apparatus according to claim 18, wherein the signal corresponding to the state of said memory cell is a bit line signal of said memory cell.

20. Apparatus according to claim 18, wherein the signal corresponding to the state of said memory cell is a bit line voltage of said memory cell.

21. Apparatus for verifying programming of an electrically alterable non-volatile memory cell having more than two predetermined memory states, comprising:

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell; and

a verifying device to detect a parameter indicating the state of said memory cell and to verify whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal.

22. Apparatus according to claim 21, wherein said parameter is a bit line signal parameter of said memory cell.

23. Apparatus according to claim 21, wherein said parameter is a bit line voltage of said memory cell.

24. Apparatus for programming an electrically alterable non-volatile memory cell having more than two predetermined memory states, comprising:

a selecting device which selects one of a plurality of predetermined reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

a programming signal source to apply a programming signal to said memory cell; and

a comparator to compare a signal corresponding to the state of said memory cell with the selected reference signal to verify whether said memory cell is programmed to the state indicated by said information.

25. Apparatus according to claim 24, wherein the signal corresponding to the state of said memory cell is a bit line signal of said memory cell.

26. Apparatus according to claim 24, wherein the signal corresponding to the state of said memory cell is a bit line voltage of said memory cell.

27. Apparatus for programming an electrically alterable non-volatile memory cell having more than two predetermined memory states, comprising:

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

a programming signal source to apply a programming signal to said memory cell; and

a verifying device to detect a parameter indicating the state of said memory cell and to verify whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal.

28. Apparatus according to claim 27, wherein said parameter is a bit line signal parameter of said memory cell.

29. Apparatus according to claim 27, wherein said parameter is a bit line voltage of said memory cell.

30. Apparatus for programming an electrically alterable non-volatile memory cell having more than two predetermined memory states, comprising:

a selecting device which selects one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

a programming signal source to apply a programming signal to said memory cell; and

a control device to control the application of said programming signal to said memory cell based on the selected reference signal.

31. Apparatus according to claim 30, wherein said control device is constructed to detect a parameter indicating the sate of said memory cell, to verify whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal, and to control the application of said programming signal to said memory cell based on a result of the verification.

32. Apparatus according to claim 30, wherein said control device is constructed to compare a signal corresponding to the state of said memory cell with the selected reference signal, and to control the application of said programming signal to said memory cell based on a result of the comparison.

33. A method of verifying programming of an electrically alterable non-volatile memory cell having more than two predetermined memory states, said method comprising:

selecting one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell; and

comparing a signal corresponding to the state of said memory cell with the selected reference signal to verify whether said memory cell is programmed to the state indicated by said information.

34. A method according to claim 33, wherein said comparing includes comparing a bit line signal of said memory cell with the selected reference signal.

35. A method according to claim 33, wherein said comparing includes comparing a bit line voltage of said memory cell with a voltage of the selected reference signal.

36. A method of verifying programming of an electrically alterable non-volatile memory cell having more than two predetermined memory states, said method comprising:

selecting one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

detecting a parameter indicating the state of said memory cell; and

verifying whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal.

37. A method according to claim 36, wherein said parameter is detected at a bit line terminal of said memory cell.

38. A method according to claim 36, wherein said parameter is a bit line voltage of said memory cell.

39. A method of programming an electrically alterable non-volatile memory cell having more than two predetermined memory states, said method comprising:

selecting one of a plurality of predetermined reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

applying a programming signal to said memory cell; and

comparing a signal corresponding to the state of said memory cell with the selected reference signal to verify whether said memory cell is programmed to the state indicated by said information.

40. A method according to claim 39, wherein said comparing includes comparing a bit line signal of said memory cell with the selected reference signal.

41. A method according to claim 39, wherein said comparing includes comparing a bit line voltage of said memory cell with a voltage of the selected reference signal.

42. A method of programming an electrically alterable non-volatile memory cell having more than two predetermined memory states, said method comprising:

selecting one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

applying a programming signal to said memory cell;

detecting a parameter indicating the state of said memory cell; and

verifying whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal.

43. A method according to claim 42, wherein said parameter is detected at a bit line terminal of said memory cell.

44. A method according to claim 42, wherein said parameter is a bit line voltage of said memory cell.

45. A method of programming an electrically alterable non-volatile memory cell having more than two predetermined memory states, said method comprising:

selecting one of a plurality of reference signals in accordance with information indicating a memory state to which said memory cell is to be programmed, each reference signal corresponding to a different memory state of said memory cell;

applying a programming signal to said memory cell; and

controlling the application of said programming signal to said memory cell based on the selected reference signal.

46. A method according to claim 45, including detecting a parameter indicating the state of said memory cell, verifying whether said memory cell is programmed to the state indicated by said information based on the detected parameter and the selected reference signal, and wherein the application of said programming signal is controlled based on a result of said verifying.

47. A method according to claim 45, including comparing a signal corresponding to the state of said memory cell with the selected reference signal, and wherein the application of said programming signal is controlled based on a result of said comparing.