Computer to microcomputer interface

• US 5,764,907 A
• Filed: 10/17/1994
• Issued: 06/09/1998
• Est. Priority Date: 10/17/1994
• Status: Expired due to Term

• Current Assignee: Chrysler Group LLC (Stellantis NV)
• Original Assignee: Chrysler Corporation (Stellantis NV)
• Inventors: Herda, Gary M., Hurley, Harlan S.
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/324,208
• Time in Patent Office: 1,331 Days
• Field of Search: 395/200, 395/287, 395/288, 395/285, 395/308, 395/856, 395/857, 395/858, 395/859, 395/200.12, 395/200.14, 395/200.19, 395/825, 395/851, 395/852, 395/853 , 395/878, 395/200.09, 395/200.42, 395/200.43, 395/200.44, 395/200.46, 395/200.47, 395/200.49
• US Class Current: 709/216
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A serial interface for facilitating communication between an outside computer and a microcontroller located on a printed circuit board enables the computer to read the contents of a RAM location or write to any RAM location in the microcontroller. The methodology used in association with this invention is preferably utilized across a two-wire asynchronous bus where one of the lines is dedicated to transmissions from the microcontroller and the other line is dedicated to transmissions from the computer to the microcontroller.

Claims

1. A method of communicating between an outside computer and a microcontroller having a random access memory, using a two wire asynchronous bus, comprising the steps of:

(A) transmitting an access signal from the computer to the microcontroller, using a first wire of the two wire asynchronous bus;

(B) determining a response step to be performed by the microcontroller, using the access signal from step (A); and

(C) performing a response step, using the microcontroller, said response step being from a group consisting of (1) loading data transmitted from the computer into the random access memory, using the first wire of the two wire asynchronous bus when the access signal indicates that the computer will write data to the random access memory;

(2) transmitting preselected contents from the random access memory to the computer, using a second wire of the two wire asynchronous bus when the access signal indicates that the computer will read data from the random access memory; and

(3) altering an operating status of the microcontroller when the access signal corresponds to a command signal.

2. The method of claim 1, wherein step (A) is performed by the substeps of:

transmitting a start byte, using the first wire of the two wire bus; and

transmitting a preselected address of the random access memory in hexadecimal format.

3. The method of claim 1, wherein step (B) is performed by the substeps of determining whether the access signal indicates that the computer will write data to the random access memory.

4. The method of claim 3, wherein step (C) is performed by performing the response step (2) from step (C).

5. The method of claim 4, wherein response step (2) is performed by the further substeps of determining a preselected address location within the random access memory indicated by the access signal, loading the preselected address into a random access memory pointer in the microcontroller and loading data into the preselected address location, said data being transmitted from the computer across the first wire.

6. The method of claim 1, wherein step (B) is performed by the substeps of determining whether the access signal indicates that the computer will read data from a preselected address location within the random access memory.

7. The method of claim 6, wherein step (C) is performed by performing the response step (1) from step (C).

8. The method of claim 7, wherein response step (1) is performed by the further substeps of determining a preselected address location within the random access memory indicated by the access signal, loading the preselected address location into a random access pointer, transmitting contents from within the preselected address location to the computer using the second wire.

9. The method of claim 1, wherein step (C) is performed by performing the response step (3) from step (C).

10. The method of claim 9, wherein response step (3) is performed by the further substeps of initializing the microcontroller when the access signal indicates that the microcontroller is to be initialized.

11. The method of claim 9, wherein response step (3) is performed by the further substeps of placing the microcontroller into a halt mode when the access signal indicates that the microcontroller is to be halted.

12. The method of claim 9, wherein response step (3) is performed by the further substeps of reading and updating keyread locations within the random access memory when the access signal indicates that the keyread locations are to be updated.

13. The method of claim 9, wherein response step (3) is performed by the further substep of ignoring all inputs from input/output pins of a printed circuit board having the microcontroller.

14. A method of interfacing an outside computer with a microcontroller on a printed circuit board, using a two wire asynchronous bus, comprising the steps of:

transmitting an access signal from the computer to the microcontroller, using a first wire of the two wire bus, the access signal dictating a response to be performed by the microcontroller;

defining a first response to be performed by the microcontroller that includes sending data from a preselected random access memory in the microcontroller to the computer, using a second wire of the two wire bus;

defining a second response to be performed by the microcontroller that includes receiving data from the computer, using the first wire, and placing the data into a preselected random access memory in the microcontroller;

determining whether the access signal dictates that the first response is to be performed;

determining whether the access signal dictates that the second response is to be performed; and

performing a response step from a set of response steps consisting of the first and second response steps.