Segmenting non-volatile memory into logical pages sized to fit groups of commonly erasable data

• US 5,765,211 A
• Filed: 10/15/1996
• Issued: 06/09/1998
• Est. Priority Date: 10/18/1995
• Status: Expired due to Term

• Current Assignee: Gemalto SA (Thales SA)
• Original Assignee: Schlumberger Industries Incorporated (Schlumberger NV)
• Inventors: Luck, Xavier
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US08/730,747
• Time in Patent Office: 602 Days
• Field of Search: 711/173, 711/171, 711/170, 711/153, 711/103, 711/209, 395/182.01
• US Class Current: 711/209
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata

Abstract

An electronic component including an electrically erasable non-volatile memory for storing information structured in logical entities that are managed by a memory manager. The memory is segmented into pages for the purpose of erasing the information. The memory manager is programmed to organize at least one type of logical entity into pages. Each of the logical entities occupies, at least in part, an integer number of pages in an exclusive manner. This technique is applicable to electronic components to which the electrical power supply is liable to be interrupted in an untimely manner.

Claims

1. A method of storing information in an electrically erasable non-volatile memory, such information being structured into logical entities, comprising the steps of:

segmenting the memory into pages, each of which includes a plurality of bits from the memory that are erasable together;

organizing at least a selected one of the logical entities into data pages sized to correspond with the memory pages;

arranging the information stored in the memory so that said at least one selected logical entity occupies, in an exclusive manner, an integer number of the memory pages.

2. The method according to claim 1, wherein, if a memory page is occupied in part by said selected logical entity, the remainder of such memory page is left blank.

3. The method according to claim 1, wherein, when a memory page is to be occupied in part by said selected logical entity, creating a derived logical entity that occupies in full all of the pages of said integer number of pages.

4. The method according to claim 1, wherein said logical entities are of the directory type.

5. The method according to claim 1, wherein said logical entities are of the file type.

6. The method according to claim 1, wherein said logical entities are of the file record type.

7. The method according to claim 1, wherein said logical entities are of the header type.

8. The method according to claim 1, wherein the organizing and arranging steps are controlled by a memory manager, and further comprising the step of implanting the memory manager in a component with said memory.

9. The method according to claim 8, wherein said memory manager is a microprocessor with a program.

10. The method according to claim 9, wherein the component is included in an electronic memory card, and said electrically erasable non-volatile memory and said microprocessor are carried by a single semiconductor chip.

11. The method according to claim 9, wherein the component is included in an electronic memory key.

12. The method according to claim 9, wherein the component is included in a PCMCIA card.

13. The method according to claim 1, wherein said electrically erasable non-volatile memory is of the EEPROM type.

14. The method according to claim 1, wherein said electrically erasable non-volatile memory is of the flash EPROM type.

15. The method according to claim 8, wherein said memory manager is suitable for detecting corruptions of information and for restoring said information.

16. The method according to claim 8, wherein the component is in electronic memory devices that are electrically powered by an external power supply system and that are liable to be disconnected in an untimely manner from said external power supply system.