SOI CMOS structure

• US 5,767,549 A
• Filed: 07/03/1996
• Issued: 06/16/1998
• Est. Priority Date: 07/03/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Wei, Sadana, Devendra Kumar, Taur, Yuan
• Primary Examiner(s): Crane, Sara W.
• Application Number:
  US08/678,442
• Time in Patent Office: 713 Days
• Field of Search: 257/347, 257/351, 257/369, 257/348, 257/349, 257/350, 257/352, 257/354, 257/507, 257/66, 257/67, 257/74, 257/75, 257/524, 257/353, 257/371
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring. The invention overcomes the problem of a floating gate due to charge accumulation below the channel of MOS FET'"'"'s.

Claims

1. An integrate circuit comprising:

a substrate of dielectric material,

a continuous sheet of single crystal semiconductor material on said substrate of dielectric material,

said continuous sheet of single crystal semiconductor material having a continuous recessed region having a first thickness,

said recessed region being patterned to leave a plurality of mesas surrounded by said recessed region,

said mesas having a second thickness greater than said first thickness,

a plurality of said mesas each having at least one field effect transistor formed thereon, each said field effect transistor having a source, drain, a channel therebetween, and a gate, wherein said second thickness is selected to permit said drain and source to form a substantially fully depleted depletion region extending to said substrate below each of said drain and source, respectively, while leaving therebetween and under said channel a neutral, partially depleted region of said recessed region for interconnection with adjoining regions of said recessed region of said continuous sheet,

said continuous sheet of single crystal semiconductor material serving as two-dimensional ohmic interconnection between at least two of said field effect transistors, said field effect transistors being of the same channel type, and

said continuous sheet of single semiconductor material having a common substrate contact for interconnecting a plurality of said field effect transistors thereto.

2. The integrated circuit of claim 1, wherein said recessed region and said plurality of mesas have a common concentration of p type doping.

3. The integrated circuit of claim 1, wherein each said field effect transistor has an n channel, a source, a gate, a gate oxide, and a body.

4. The integrate circuit of claim 1, further including a plurality of sheets of single crystal semiconductor material spaced apart on said layer of dielectric material.

5. The integrated circuit of claim 4, wherein at least one of said plurality of sheets is coupled electrically through a switch to another of said plurality of sheets.