Interrupt-based hardware support for profiling memory system performance

• US 5,768,500 A
• Filed: 11/14/1996
• Issued: 06/16/1998
• Est. Priority Date: 06/20/1994
• Status: Expired due to Term

• Current Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Goldberg, Aaron Jay, Agrawal, Prathima, Trotter, John Andrew
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Coulter, Kenneth R.
• Application Number:
  US08/749,043
• Time in Patent Office: 579 Days
• Field of Search: 395/704, 395/184.01, 371/21.1
• US Class Current: 714/47.2
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 2201/805 Real-time
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches

Abstract

Fueled by higher clock rates and superscalar technologies, growth in processor speed continues to outpace improvement in memory system performance. Reflecting this trend, architects are developing increasingly complex memory hierarchies to mask the speed gap, compiler writers are adding locality enhancing transformations to better utilize complex memory hierarchies, and applications programmers are re-coding their algorithms to exploit memory systems. All of these groups need empirical data on memory behavior to guide their optimizations. This paper describes how to combine simple hardware support and sampling techniques to obtain such data without appreciably perturbing system performance. By augmenting a cache miss counter with a compare register and interrupt line such that the processor is interrupted when the counter matches the compare value, we can sample system state and develop cache miss profiles that associate cache misses with specific processes, procedures, call stacks, addresses, or user defined aspects of system state. This idea is implemented in the Mprof prototype that profiles data stall cycles, first level cache misses, and second level misses on the sun Sparc 10/41. Simple case studies are provided to illustrate Mprof'"'"'s features.

Claims

1. A system for profiling the behavior of memory systems in a processor, comprising:

an event detector configured to generate a detection signal upon an occurrence of a predetermined data stall time event;

a counter, coupled to said event detector, configured to receive and count occurrences of said detection signal received from said event detector, said counter further configured to generate a pulse signal when a predetermined count value of said detection signal occurrences is reached;

an interrupt generator, coupled to said counter, configured to generate a profiling interrupt signal upon receipt of said pulse signal; and

an interrupt handler residing in the processor, configured to record a state of the processor relating to the memory access data stall time event upon receipt of said profiling interrupt signal generated by said interrupt generator.

2. The system of claim 1, wherein said event detector, said interrupt generator, and said counter are implemented in one or more programmable array, logic chips.

3. The system of claim 1, wherein said counter is a down counter, said down counter generating said pulse signal when said count value is zero.

4. The system of claim 1, wherein said counter is loadable counter, said loadable counter being selectively reset by said interrupt handler at least during one run of a single currently executing process.

5. The system of claim 1, wherein the memory system resides in a Sun SPARC 10/41 workstation.

6. The system of claim 1, wherein said event detector monitors a memory bus and outputs said detection signal when a main memory read signal is received to detect second level cache misses.

7. The system of claim 1, wherein said counter comprises a reset input configured to enable an external reset signal to reset said down counter.

8. The system of claim 1, wherein said counter comprises an enable input configured to enable an external enable signal to enable said down counter.

9. The system of claim 1, wherein said event detector detects data cache stall time, said counter counting a number of clock cycles during which said event detector receives a cache stall signal, said cache stall signal having a predetermined value when the processor is waiting on a data cache.

10. The system of claim 1, wherein said event detector detects primary cache misses and second level cache misses.

11. The system of claim 1, wherein said counter further comprises an enable input, said counter configured to count said event when said enable bit is set.

12. A performance monitor system for simultaneous profiling of multiple conditions in a processor memory system, comprising:

a plurality of condition detectors, each of said plurality of condition detectors configured to monitor a predetermined data stall time condition and to generate a detection signal upon an occurrence of said predetermined condition;

a plurality of counters, each of said plurality of counters coupled to a respective one of said plurality of condition detectors, for receiving said detection signal and for generating a count signal indicating the number of said detection signals received;

a plurality of loadable compare registers, each of said plurality of loadable compare registers coupled to a respective one of said plurality of counters, configured to receive said count signal from said respective counter and for comparing said count signal to a predetermined value loaded in said each of said plurality of compare registers;

an interrupt generator, coupled to each of said plurality of comparators, configured to generate a profiling interrupt signal based upon a predetermined relationship between said pulse signals received from said plurality of comparators; and

an interrupt handler, residing in the processor, configured to record a state of the processor relating to the memory access data stall time event upon receipt of said profiling interrupt signal generated by said interrupt generator.

13. The system of claim 12, wherein the performance monitor is implemented in a field programmable gate array.

14. The system of claim 12, wherein each of said plurality of counters comprises an enable input, said enable input enabling each of said plurality of counters to count said event when said enable bit is set.

15. A method for profiling the behavior of memory systems in a processor, comprising:

generating a detection signal upon an occurrence of a predetermined data stall time event;

counting occurrences of said detection signal received from said event detector, and generating a pulse signal when a predetermined count value of said detection signal occurrences is reached;

generating a profiling interrupt signal upon receipt of said pulse signal; and

recording a state of the processor relating to the memory access data stall time event upon receipt of said profiling interrupt signal.