SOI substrate having a high heavy metal gettering effect for semiconductor device

• US 5,773,152 A
• Filed: 10/13/1995
• Issued: 06/30/1998
• Est. Priority Date: 10/13/1994
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Okonogi, Kensuke
• Primary Examiner(s): SPEER, TIMOTHY M
• Application Number:
  US08/543,068
• Time in Patent Office: 991 Days
• Field of Search: 257/66, 257/67, 257/70, 257/347, 257/349, 257/353, 428/446, 428/448, 428/700, 428/701, 428/702
• US Class Current: 428/446
• CPC Class Codes: H01L 21/3226 of silicon on insulator
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

An SOI substrate comprises a buried silicon oxide layer formed directly under an active silicon layer, and a layer containing phosphorus therein formed under the buried silicon oxide layer. The layer containing phosphorus therein acts as the getter layer, so that an effective gettering of heavy metals can be obtained in a wide temperature range from a low temperature region to a high temperature region. In addition, since the silicon oxide layer exists between the active layer and the getter layer, the diffusion of the phosphorus into the active layer is effectively prevented, and therefore, the phosphorus scarely diffuses to the active layer, so that the device manufactured is subjected to almost no adverse influence of the diffusion of the phosphorus.

Claims

1. A silicon-on-insulator substrate comprising an active silicon layer, a buried silicon oxide layer formed directly under said active silicon layer, and an impurity layer containing a high concentration of impurity therein and formed under said buried silicon oxide layer.

2. A silicon-on-insulator substrate claimed in claim 1 wherein said impurity layer is formed of a silicon layer containing a high concentration of impurity therein.

3. A silicon-on-insulator substrate claimed in claim 2 further including a silicon substrate layer between said buried silicon oxide layer and said impurity layer.

4. A silicon-on-insulator substrate claimed in claim 2 further including a silicon substrate layer formed under said impurity layer.

5. A silicon-on-insulator substrate claimed in claim 1 wherein said impurity layer is formed of a polysilicon layer containing a high concentration of impurity therein.

6. A silicon-in-insulator substrate claimed in claim 5 further including a silicon substrate layer between said buried silicon oxide layer and said impurity layer.

7. A silicon-on-insulator substrate claimed in claim 5 further including a silicon substrate layer formed under said impurity layer.

8. A silicon-on-insulator substrate claimed in claim 1 wherein said impurity layer is formed of a silicon oxide layer containing a high concentration of impurity therein.

9. A silicon-on-insulator substrate claimed in claim 8 further including a silicon substrate layer formed under said impurity layer.

10. A silicon-on-insulator substrate claimed in claim 1 wherein said impurity layer is formed of an N-type silicon substrate containing a high concentration of impurity therein.

11. A silicon-on-insulator substrate claimed in claim 1 wherein said impurity layer has a plurality of recesses formed on an upper surface thereof, and said silicon oxide layer is formed to cover said upper surface of said impurity layer including said plurality of recesses, and wherein said active silicon layer is divided into a plurality of active regions each located in and partitioned by one of said plurality of island-like recesses.

12. A silicon-on-insulator substrate claimed in claim 1 wherein said impurity contained in said impurity layer is one selected from the group consisting of phosphorus, boron and arsenic.