High frequency semiconductor component

• US 5,773,887 A
• Filed: 06/20/1997
• Issued: 06/30/1998
• Est. Priority Date: 06/03/1996
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Vassar, William M., Pavio, Anthony M.
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): Wilson, Allan R.
• Application Number:
  US08/879,453
• Time in Patent Office: 375 Days
• Field of Search: 257/698, 257/725, 257/728, 257/774, 257/776, 257/275, 257/276, 257/277, 257/664, 333/246, 333/247
• US Class Current: 257/728
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A high frequency semiconductor component (10) includes a first substrate (12) having a first surface (13) opposite a second surface (14), a first electrically conductive layer (16) supported by the first surface (13) of the first substrate (12), a second electrically conductive layer (17) supported by the second surface (14) of the first substrate (12) wherein the second electrically conductive layer (17) is electrically coupled to the first electrically conductive layer (16), a second substrate (19) having a first surface (20) and a second surface (21), a third electrically conductive layer (22) supported by the first surface (20) of the second substrate (19), and an electrically insulating layer (23) between the second and third electrically conductive layers (17, 22) wherein the second and third electrically conductive layers (17, 22) are electrically coupled together through the electrically insulating layer (23).

Claims

1. A high frequency semiconductor component comprising:

a first substrate having a first surface opposite a second surface, the first substrate comprised of a semiconductor substrate, the first and second surfaces at opposites sides of the semiconductor substrate;

a first transmission line supported by the first surface of the first substrate;

an integrated circuit supported by and located at least partially within the first surface of the first substrate, the integrated circuit electrically coupled to the first transmission line;

a second transmission line supported by the second surface of the first substrate, the second transmission line electrically coupled to the first transmission line by a d.c. connection;

a second substrate having a first surface and a second surface wherein the first surface faces towards the second surface of the first substrate;

a third transmission line supported by the first surface of the second substrate and underlying the second transmission line; and

an electrically insulating layer between the second and third transmission lines, the second and third transmission lines capable of being electrically coupled together by a high frequency signal through the electrically insulating layer, the second and third transmission lines devoid of a d.c. connection with each other.

2. The high frequency semiconductor component of claim 1 wherein the electrically insulating layer is continuous beneath the second transmission line.

3. The high frequency semiconductor component of claim 1 wherein the second transmission line has a length and wherein the length of the second transmission line overlies a portion of the third transmission line.

4. The high frequency semiconductor component of claim 1 further comprising:

a ground plane supported by the second surface of the first substrate, the ground plane devoid of a d.c. connection with the second transmission line, the ground plane coplanar with the second transmission line; and

two additional transmission lines supported by the first surface of the second substrate, the two additional transmission lines devoid of a d.c. connection with the ground plane and the third transmission line wherein the electrically insulating layer is between the two additional transmission lines and the ground plane wherein the two additional transmission lines underlie a portion of the ground plane wherein the two additional transmission lines are capable of being electrically coupled to the ground plane by a high frequency signal through the electrically insulating layer wherein a first one of the two additional transmission lines is adjacent to a first side of the third transmission line wherein a second one of the two additional transmission lines is adjacent to a second side of the third transmission line and wherein the two additional transmission lines are coplanar with the third transmission line.

5. The high frequency semiconductor component of claim 4 wherein the second transmission line has a length and wherein each of the two additional transmission lines have a length and wherein the length of the second transmission line is approximately equal to each of the lengths of the two additional transmission lines.

6. The high frequency semiconductor component of claim 5 wherein each of the two additional transmission lines has a width and wherein the length of the second transmission line is approximately equal to each of the widths of the two additional transmission lines.

7. A semiconductor component comprising:

a first substrate having a first surface, a second surface, and a side surface wherein the side surface couples the first and second surfaces, wherein the first substrate is comprised of a semiconductor substrate, and wherein the first and second surfaces are located at opposite sides of the semiconductor substrate;

a semiconductor device supported by and located at least partially within the first surface of the first substrate;

a first electrically conductive layer coupled to the first surface of the first substrate, the first electrically conductive layer electrically coupled to the semiconductor device;

a second electrically conductive layer coupled to a first portion of the second surface of the first substrate, the second electrically conductive layer electrically coupled to the first electrically conductive layer; and

a third electrically conductive layer coupled to a second portion of the second surface of the first substrate, the third electrically conductive layer devoid of a d.c. connection with the first and second electrically conductive layers, the third electrically conductive layer having a hole wherein the second electrically conductive layer is located in the hole.

8. The semiconductor component of claim 7 further comprising:

a second substrate having a first surface, a second surface, and a side surface wherein the side surface of the second substrate couples the first and second surfaces of the second substrate;

a fourth electrically conductive layer coupled to a portion of the first surface of the second substrate, the second electrically conductive layer overlying a portion of the fourth electrically conductive layer, the fourth electrically conductive layer devoid of a d.c. connection with the first, second, and third electrically conductive layers;

a fifth electrically conductive layer coupled to a different portion of the first surface of the second substrate, the fifth electrically conductive layer devoid of a d.c. connection with the first, second, and fourth electrically conductive layers, the fifth electrically conductive layer underlying a portion of the third electrically conductive layer;

a sixth electrically conductive layer coupled to the second surface of the second substrate, the sixth electrically conductive layer electrically coupled to the fifth electrically conductive layer, the sixth electrically conductive layer devoid of a d.c. connection with the first, second, and fourth electrically conductive layers; and

an electrically insulating layer between the second and fourth electrically conductive layers and between the third and fifth electrically conductive layers and between the first and second substrates, the second and fourth electrically conductive layers capable of being electrically coupled together by a high frequency current through the electrically insulating layer, the third and fifth electrically conductive layers capable of being electrically coupled together by another high frequency current through the electrically insulating layer.

9. The semiconductor component of claim 8 wherein the electrically insulating layer is devoid of a via.

10. The semiconductor component of claim 7 wherein the first substrate has a via and wherein the first and second electrically conductive layers are electrically coupled together through the via.

11. The semiconductor component of claims 7 further comprising a fourth electrically conductive layer coupled to the side surface of the first substrate wherein the fourth electrically conductive layer electrically couples the first electrically conductive layer to the second electrically conductive layer.

12. A semiconductor component comprising:

a semiconductor substrate having a first surface and a second surface wherein the first and second surfaces are opposite each other;

a semiconductor device in the first surface of the semiconductor substrate;

a first metal layer electrically coupled to the semiconductor device, the first metal layer adjacent to the first surface of the semiconductor substrate;

an additional substrate having a first surface and a second surface, the first surface of the additional substrate facing towards the second surface of the semiconductor substrate, the additional substrate comprised of an other semiconductor substrate wherein the first and second surfaces of the additional substrate are at opposite sides of the other semiconductor substrate;

a second metal layer adjacent to the first surface of the additional substrate, the second metal layer under the second surface of the semiconductor substrate, the second metal layer under a portion of the first metal layer;

a third metal layer adjacent to the second surface of the semiconductor substrate, the third metal layer devoid of a d.c. connection with the first and second metal layers, the third metal layer having a hole under the first metal layer to permit electrical coupling between the first and second metal layers;

a dielectric layer located between the second metal layer and the third metal layer and between the first surface of the additional substrate and the second surface of the semiconductor substrate, the second metal layer electrically coupled to the first metal layer through the semiconductor substrate and through the dielectric layer, the first and second metal layers;

a fourth metal layer adjacent to the second metal layer and the first surface of the additional substrate, the fourth metal layer devoid of a d.c. connection with the first and second metal layers wherein the dielectric layer is between the third and fourth metal layers and wherein the fourth metal layer is electrically coupled to the third metal layer by a high frequency signal through the dielectric layer.

13. The semiconductor component of claim 12 further comprising a fifth metal layer adjacent to the third metal layer and the second surface of the semiconductor substrate, the fifth metal layer overlying a portion of the second metal layer, a portion of the fifth metal layer in the hole of the third metal layer, the fifth metal layer devoid of a d.c. connection with the second, third, and fourth metal layers, the fifth metal layer electrically coupled to the first metal layer wherein a portion of the dielectric layer is located between the second and fifth metal layers wherein the fifth metal layer is electrically coupled to the second metal layer through the portion of the dielectric layer by a high frequency signal and wherein the portion of the dielectric layer is continuous.

14. The semiconductor component of claim 13 wherein the semiconductor substrate has a via extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate and wherein the fifth metal layer is electrically coupled to the first metal layer through the via.

15. The semiconductor component of claim 12 wherein the fourth metal layer has a length and a width wherein the length is approximately equal to the width.

16. The semiconductor component of claim 12 further comprising a fifth metal layer adjacent to the second surface of the additional substrate, the fifth metal layer electrically coupled to the fourth metal layer.

17. The semiconductor component of claim 12 wherein the fourth metal layer has a length of approximately one quarter of a wavelength of an operating frequency of the semiconductor device and wherein the hole in the third metal layer has a length of approximately one quarter of a wavelength of an operating frequency of the semiconductor device.

18. The semiconductor component of claim 13 wherein the fourth metal layer has a length and a width of approximately one quarter of a wavelength of an operating frequency of the semiconductor device and wherein the fifth metal layer has a length of approximately equal to the length of the fourth metal layer.