Digital clock recovery loop

• US 5,774,022 A
• Filed: 08/29/1996
• Issued: 06/30/1998
• Est. Priority Date: 08/29/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation), Micron Communications, Inc. (Micron Technology, Inc.)
• Inventors: O'Toole, James E., Pax, George E., Griffin, Dan M.
• Primary Examiner(s): Mis, David
• Application Number:
  US08/707,220
• Time in Patent Office: 670 Days
• Field of Search: 331/1 A, 331/4, 331/8, 331/17, 331/25, 331/DIG. 2, 327/43, 327/156-159, 375/376
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Claims

1. A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:

a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node;

charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator;

a start-up circuit that performs frequency discrimination and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and

a state machine that performs phase control and adjusts the voltage on the control node of the voltage controlled oscillator.

2. A communications system in accordance with claim 1 and further comprising bias circuitry applying an offset voltage to the voltage controlled oscillator such that, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency of the voltage controlled oscillator when frequency lock is established.

3. A communications system in accordance with claim 1 wherein the state machine makes finer adjustments to the voltage on the control node of the voltage controlled oscillator than the start-up circuit.

4. A communications system in accordance with claim 1 wherein the start-up circuit is a digital circuit.

5. A communications system in accordance with claim 1 wherein the state machine is implemented by digital circuitry.

6. A communications system in accordance with claim 1 wherein the clock recovery circuit varies the output of the voltage controlled oscillator until a predetermined number of transitions of the output fit within a time interval of an identifiable discrete segment of the incoming data.

7. A communications system in accordance with claim 1 wherein the incoming data is direct spread spectrum data including a plurality of chips, and wherein clock recovery circuit varies the output of the voltage controlled oscillator until a predetermined number of transitions of the output fit within a time interval of a predetermined number of chips in the incoming data.

8. A clock recovery circuit that extracts a clock signal from an input digital signal, the clock recovery circuit comprising:

a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node;

charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator;

a start-up circuit that performs frequency discrimination and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and

a state machine that performs phase control and adjusts the voltage on the control node of the voltage controlled oscillator.

9. A clock recovery circuit in accordance with claim 8 and further comprising bias circuitry applying an offset voltage to the voltage controlled oscillator such that, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency of the voltage controlled oscillator when frequency lock is established.

10. A clock recovery circuit in accordance with claim 8 wherein the state machine makes finer adjustments to the voltage on the control node of the voltage controlled oscillator than the start-up circuit.

11. A clock recovery circuit in accordance with claim 8 wherein the start-up circuit is a digital circuit.

12. A clock recovery circuit in accordance with claim 8 wherein the state machine is implemented by digital circuitry.

13. A clock recovery circuit in accordance with claim 8 wherein the input digital signal is direct spread spectrum data including a plurality of chips, and wherein clock recovery circuit varies the output of the voltage controlled oscillator until a predetermined number of transitions of the output fit within a time interval of a predetermined number of chips in the incoming data.

14. A phase lock loop receiving an oscillating input signal and producing an output signal, the phase lock loop comprising circuitry including a plurality of flip-flops which are chained together and used to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal, wherein the input signal is digital and the phase locked loop extracts a clock from the digital signal, the phase locked loop further comprising a control node, and a state machine that performs phase control and adjusts the voltage on the control node of the voltage controlled oscillator.

15. A communications system in accordance with claim 14 wherein the circuitry including the flip-flops makes adjustments to the voltage on the control node, and wherein the state machine makes finer adjustments to the voltage on the control node of the voltage controlled oscillator than the circuitry including the flip-flops.

16. A communications system in accordance with claim 14 and further comprising bias circuitry applying an offset voltage to the voltage controlled oscillator such that, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency of the voltage controlled oscillator when frequency lock is established.

17. A communications system including a clock recovery circuit for extracting a clock signal from incoming digital data, the clock recovery circuit comprising:

a voltage controlled oscillator having a control node and having an output configured to produce an output wave having a frequency that varies in response to a voltage applied to the control node;

charge pump and loop filter circuitry configured to control the rate of change of the voltage on the control node of the voltage controlled oscillator;

a start-up circuit configured to perform frequency discrimination and, in conjunction with the charge pump and loop filter circuitry, adjust the voltage on the control node of the voltage controlled oscillator; and

a state machine configured to perform phase control and adjust the voltage on the control node of the voltage controlled oscillator.

18. A communications system in accordance with claim 17 and further comprising bias circuitry configured to apply an offset voltage to the voltage controlled oscillator such that, in operation, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency of the voltage controlled oscillator when frequency lock is established.