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Methods to enhance SOI SRAM cell stability

  • US 5,774,411 A
  • Filed: 09/12/1996
  • Issued: 06/30/1998
  • Est. Priority Date: 09/12/1996
  • Status: Expired due to Fees
First Claim
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1. A silicon-on-insulator static logic device includingan array of controlled elements,transfer gate means connected to respective ones of word lines and bit lines for controlling connection of each of said controlled elements to respective ones of said bit lines, andmeans for limiting peak parasitic bipolar transient discharge current through a respective transfer gate means from a node of respective deselected ones of said controlled elements.

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