Methods to enhance SOI SRAM cell stability
First Claim
1. A silicon-on-insulator static logic device includingan array of controlled elements,transfer gate means connected to respective ones of word lines and bit lines for controlling connection of each of said controlled elements to respective ones of said bit lines, andmeans for limiting peak parasitic bipolar transient discharge current through a respective transfer gate means from a node of respective deselected ones of said controlled elements.
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Abstract
Modifications of a digital logic device, such as a static or dynamic random access memory (SRAM or DRAM) or pass gate logic circuit or the like, implemented with complementary metal-oxide-semiconductor (CMOS) structures formed with silicon-on-insulator (SOI or, more specifically, SOICMOS) technology effectively suppress transient parasitic bipolar current disturbances (e.g. transient half select write disturb instabilities) caused by a discharge current through a parasitic lateral bipolar transistor formed under the transfer gate field effect transistors. Level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time even though level shifting can greatly increase majority carrier density in the floating body (gate) of a SOICMOS transistor at a particular level shifted voltage range. Alternatively, or additionally, the discharge of deselected cells can be slowed to avoid instability by increasing resistance of the transistors in the data buffer (with saving of chip space) and/or increasing bit line capacitance by increasing bit line length (allowing increased memory array size or an additional cell array on a chip).
195 Citations
20 Claims
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1. A silicon-on-insulator static logic device including
an array of controlled elements, transfer gate means connected to respective ones of word lines and bit lines for controlling connection of each of said controlled elements to respective ones of said bit lines, and means for limiting peak parasitic bipolar transient discharge current through a respective transfer gate means from a node of respective deselected ones of said controlled elements.
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17. A method of suppressing transient parasitic bipolar current disturbances in a silicon-on-insulator integrated circuit when a word line is deselected and a bit line is selected including the steps of
precharging bit lines connected to controlled elements included in said silicon-on-insulator integrated circuit, and limiting peak parasitic bipolar transient current from a deselected controlled element during discharge of one of said bit lines.
Specification