Switch attenuator

• US 5,777,530 A
• Filed: 01/23/1997
• Issued: 07/07/1998
• Est. Priority Date: 01/31/1996
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakatuka, Tadayoshi
• Primary Examiner(s): GENSLER, PAUL L
• Application Number:
  US08/788,036
• Time in Patent Office: 530 Days
• Field of Search: 333/101, 333/103, 333/104, 333/81 R, 333/81 A, 455/78-83, 327/403, 327/404, 327/407-409, 327/415, 327/416
• US Class Current: 333/104
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H01Q 21/0025 Modular arrays
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

The switch attenuator of the invention includes: a first terminal connected to an antenna; a second terminal connected to a transmitter; and a third terminal connected to a receiver, thereby switching a first state and a second state. In the first state, the first terminal is connected to the second terminal, the first terminal is electrically isolated from the third terminal, the third terminal is connected to a ground and the switch attenuator is electrically controllable so as to vary an attenuation amount between the first terminal and the second terminal while maintaining such a relationship that an impedance Z1 viewed from the first terminal is substantially equal to an impedance Z2 viewed from the second terminal, and in the second state, the first terminal is connected to the third terminal, the first terminal is electrically isolated from the second terminal, the second terminal is connected to a ground and the switch attenuator is electrically controllable so as to vary an attenuation amount between the first terminal and the third terminal, while maintaining such a relationship that the impedance Z1 viewed from the first terminal is substantially equal to an impedance Z3 viewed from the third terminal.

Claims

1. A switch attenuator comprising:

a first terminal connected to an antenna;

a second terminal connected to a transmitter; and

a third terminal connected to a receiver, thereby switching a first state and a second state,

wherein in the first state,

the first terminal is connected to the second terminal,

the first terminal is electrically isolated from the third terminal,

the third terminal is connected to a ground and

the switch attenuator is electrically controllable so as to vary an attenuation amount between the first terminal and the second terminal, while maintaining such a relationship that an impedance Z1 viewed from the first terminal is substantially equal to an impedance Z2 viewed from the second terminal,

and wherein in the second state,

the first terminal is connected to the third terminal,

the first terminal is electrically isolated from the second terminal,

the second terminal is connected to a ground and

the switch attenuator is electrically controllable so as to vary an attenuation amount between the first terminal and the third terminal, while maintaining such a relationship that the impedance Z1 viewed from the first terminal is substantially equal to an impedance Z3 viewed from the third terminal.

2. A switch attenuator according to claim 1 wherein a first transistor is provided between the first terminal and a ground,

a second transistor is provided between the second terminal and the ground,

a third transistor is provided between the third terminal and the ground,

a fourth transistor is provided between the first terminal and the second terminal and

a fifth transistor is provided between the first terminal and the third terminal;

and wherein in the first state,

the third transistor is in ON state and

the fifth transistor is in OFF state,

and wherein in the second state,

the third transistor is in ON state and

the fifth transistor is in OFF state.

3. A switch attenuator according to claim 1 wherein the impedance Z1 is substantially included within a range from 0.5×

ZA to 2.0×

ZA,

the impedance Z2 is substantially included within a range from 0.5×

ZT to 2.0×

ZT and

the impedance Z3 is substantially included within a range from 0.5×

ZR to 2.0×

ZR,

where ZA, ZT and ZR denote impedances of the antenna, the transmitter and the receiver respectively.

4. A switch attenuator according to claim 3 wherein each of the first, second, third, fourth and fifth transistors is a dual-gate field effect transistor having a drain, a source and two gates, one of the two gates being connected to the drain, the other of the two gates being connected to the source and

each of the two gates receiving a voltage for an electrical control via a corresponding resistance.

5. A switch attenuator comprising:

a first terminal connected to a first antenna;

a second terminal connected to a transmitter;

a third terminal connected to a receiver; and

a fourth terminal connected to a second antenna, thereby switching a first state, a second state, a third state and a fourth state,

wherein in the first state,

the first terminal is connected to the second terminal and is electrically isolated from the third terminal,

the third terminal is connected to a ground,

the fourth terminal is electrically isolated from the first, second and third terminals and the ground and

the switch attenuator is electrically controllable so as to vary an attenuation amount between the first terminal and the second terminal, while maintaining such a relationship that an impedance Z1 viewed from the first terminal is substantially equal to an impedance Z2 viewed from the second terminal,

and wherein in the second state,

the first terminal is connected to the third terminal and is electrically isolated from the second terminal,

the second terminal is connected to a ground,

the fourth terminal is electrically isolated from the first, second and third terminals and the ground and

the switch attenuator is electrically controllable so as to vary an attenuation amount between the first terminal and the third terminal, while maintaining such a relationship that the impedance Z1 viewed from the first terminal is substantially equal to an impedance Z3 viewed from the third terminal,

and wherein in the third state,

the fourth terminal is connected to the second terminal and is electrically isolated from the third terminal,

the third terminal is connected to the ground,

the first terminal is electrically isolated from the second, third and fourth terminals and the ground and

the switch attenuator is electrically controllable so as to vary an attenuation amount between the fourth terminal and the second terminal, while maintaining such a relationship that an impedance Z4 viewed from the fourth terminal is substantially equal to the impedance Z2 viewed from the second terminal,

and wherein in the fourth state,

the fourth terminal is connected to the third terminal and is electrically isolated from the second terminal,

the second terminal is connected to the ground

the first terminal is electrically isolated from the second, third and fourth terminals and the ground and

the switch attenuator is electrically controllable so as to vary an attenuation amount between the fourth terminal and the third terminal, while maintaining such a relationship that the impedance Z4 viewed from the fourth terminal is substantially equal to the impedance Z3 viewed from the third terminal.

6. A switch attenuator according to claim 5 wherein a first transistor is provided between the first terminal and a ground,

a second transistor is provided between the second terminal and the ground,

a third transistor is provided between the third terminal and the ground,

a fourth transistor is provided between the first terminal and the second terminal

a fifth transistor is provided between the first terminal and the third terminal,

a sixth transistor is provided between the fourth terminal and a ground,

a seventh transistor is provided between the second terminal and the fourth terminal and

an eighth transistor is provided between the third terminal and the fourth terminal,

and wherein in the first state,

the third transistor is in ON state and

the fifth, sixth, seventh and eighth transistors are in OFF state,

and wherein in the second state,

the second transistor is in ON state and

the fourth, sixth, seventh and eighth transistors are in OFF state,

and wherein in the third state,

the third transistor is in ON state and

the first, fourth, fifth and eighth transistors are in OFF state,

and wherein in the fourth state,

the second transistor is in ON state and

the first, fourth, fifth and seventh transistors are in OFF state.

7. A switch attenuator according to claim 5 wherein the impedances Z1 and Z4 are substantially included within a range from 0.5×

ZA to 2.0×

ZA,

the impedance Z2 is substantially included within a range from 0.5×

ZT to 2.0×

ZT and

the impedance Z3 is substantially included within a range from 0.5×

ZR to 2.0×

ZR,

where ZA, ZT and ZR denote impedance of the antenna, the transmitter and the receiver respectively.

8. A switch attenuator according to claim 7, being formed so as to be integrated on a semiconductor substrate.

9. A switch attenuator according to claim 8, further comprising a power amplifier, the power amplifier being formed so as to be integrated on the semiconductor substrate.

10. A switch attenuator according to claim 9, further comprising a low noise amplifier, the low noise amplifier being formed so as to be integrated on the semiconductor substrate.