Floating gate memory device and method for terminating a program load cycle upon detecting a predetermined address/data pattern

• US 5,778,440 A
• Filed: 02/16/1996
• Issued: 07/07/1998
• Est. Priority Date: 10/26/1994
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hung, Chung-Hsiung, Wan, Ray-Lin, Shone, Fuchia, Cheng, Yao-Wu, Yiu, Tom Dang-Hsing
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/596,380
• Time in Patent Office: 872 Days
• Field of Search: 395/430, 395/494, 395/481, 395/421.07, 395/834, 365/185.11, 365/185.29, 365/185.33, 711/103, 711/167, 711/154, 711/217
• US Class Current: 711/154
• CPC Class Codes: G08G 1/017 identifying vehicles G08G1/015, G08G1/054 take precedence
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry. Alternatively, the pattern comprises a command address which is outside the address field of the memory array. The command address may include all or only a high order segment of the actual data address. The floating gate memory includes a state machine which automatically programs and verifies programming of the block of data after the last segment of the block is detected, and may comprise a flash memory or electrically erasable programmable read only memory (EEPROM).

Claims

1. An integrated circuit memory, comprising:

an array of storage elements;

input/output circuitry, having inputs to receive addresses and data and coupled to the array, to read and store data segments in the array in response to the addresses and the data on the inputs; and

command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and the data received at the input/output circuitry.

2. The memory of claim 1, wherein the pattern includes consecutive matching addresses, and the command logic includes a store for an address and a comparator to compare a received address with the address in the store.

3. The memory of claim 1, wherein the pattern includes consecutive matching addresses and consecutive matching data segments, and the command logic includes a store for an address and a data segment and a comparator to compare a received address and a received data segment with an address and a data segment in the store.

4. The memory of claim 1, wherein locations for data to be stored in the array are identified by addresses within an address range, and the pattern includes a command address outside the address range, and the command logic includes a store for the command address and a comparator to match a received address with the command address in the store.

5. The memory of claim 1, wherein locations for data to be stored in the array are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a high order segment and a low order segment, and the pattern includes a start command, supplied in the high order segment, comprising a bit pattern outside the address range, supplied after loading of the block of data into the array of storage elements.

6. The memory of claim 1, wherein locations for data to be stored in the array are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a high order segment and a low order segment, and the pattern includes a load command, supplied in the high order segment, comprising a bit pattern outside the address range, supplied during loading of the block of data into the array of storage elements.

7. The memory of claim 6, wherein the pattern includes changing the high order segment of the received address from the load command to the value within the address range while loading a last data segment in the sequence.

8. The memory of claim 1, wherein the array comprises floating gate memory cells.

9. The memory of claim 1, wherein the command logic includes a state machine which automatically programs and verifies programming of the block of data after the last segment in the block is detected.

10. The memory of claim 1, wherein the array comprises floating gate memory cells, and the input/output circuitry includes a state machine, responsive to the command logic, which automatically programs and verifies programming of the block of data after the last segment in the block is detected.

11. The memory of claim 10, wherein the input/output circuitry includes program/erase voltage sources coupled to the state machine which apply potentials to the floating gate cells which cause Fowler-Nordheim tunneling in cells to be programmed.

12. The memory of claim 10, wherein the input/output circuitry includes program/erase voltage sources coupled to the state machine which apply potentials to the floating gate cells which cause hot electron injection in cells to be programmed.

13. The memory of claim 1, wherein the input/output circuitry receives a control signal establishing timing for the sequence of addresses and data segments, the command logic includes logic to detect a pulse in the control signal having a characteristic pulse width indicating that the block is loaded, wherein the logic includes a state machine, responsive to the command logic, which automatically programs and verifies programming of the block of data after the last segment in the block or the pulse is detected.

14. The memory of claim 1, wherein the pattern comprises an address transition in the sequence of addresses and data segments received at the input/output circuitry.

15. A floating gate memory circuit on a semiconductor substrate comprising:

a memory array including at least M rows and N columns of floating gate cells;

M word lines, each coupled to the floating gate cells in one of the M rows of floating gate cells;

a plurality of bit lines, each coupled to the floating gate cells in at least one of the N columns of floating gate cells;

input/output circuitry, having inputs to receive addresses and data;

command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and data received at the input/output circuitry;

a page buffer, coupled to the input/output circuitry to store the block of data and supply the block of data to the N columns of floating gate cells;

write control circuitry, coupled to the command logic, the page buffer and the M word lines, which after detection of the last segment in the block, supplies programming voltages to a selected word line for programming input data to a row of floating gate cells accessed by the selected word line in response to the block of data stored in the page buffer; and

program verify circuitry, coupled to the page buffer, which verifies that floating gate cells are programmed with the block of data in the page buffer.

16. The floating gate memory circuit of claim 15, wherein the page buffer includes a plurality of bit latches coupled to corresponding ones of the plurality of bit lines, and the program verify circuitry, coupled to the bit lines, resets a bit latch to a first binary value when stored data in a floating gate cell on a corresponding bit line matches a second binary value.

17. The floating gate memory circuit of claim 15, wherein:

a row of N columns of floating gate cells includes a first page of floating gate cells and a second page of floating gate cells; and

the page buffer supplies input data to a page of floating gate cells.

18. The floating gate memory circuit of claim 16, wherein the program verify circuitry includes logic responsive to stored data from the floating gate cells and to data in the page buffer to provide a program verify signal when all programmed floating gate cells pass program verify.

19. The floating gate memory circuit of claim 16, wherein the program verify circuitry generates a program verify signal when all bit latches store the first binary value.

20. The floating gate memory circuit of claim 19, wherein the write control circuitry applies a word line program potential to a word line coupled to a selected set of floating gate cells, and a bit line program potential to bit lines coupled to bit latches storing the second binary value.

21. The floating gate memory circuit of claim 15, wherein the pattern includes consecutive matching addresses, and the command logic includes a store, coupled to the input/output circuitry, to hold an address and a comparator, coupled to the input/output circuitry, to compare a currently received address with a previously received address held in the store.

22. The floating gate memory circuit of claim 15, wherein the pattern includes consecutive matching addresses and consecutive matching data segments, and the command logic includes a store, coupled to the input/output circuitry, to hold an address and a data segment and a comparator, coupled to the input/output circuitry, to compare a currently received address and data segment with a previously received address and data segment held in the store.

23. The floating gate memory circuit of claim 15, wherein locations in the array are identified by addresses within an address range, and the pattern includes a command address outside the address range, and the command logic includes a store for the command address and a comparator, coupled to the input/output circuitry, to compare a received address with the command address in the store.

24. The floating gate memory circuit of claim 15, wherein locations for data to be stored are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a page address segment and a page buffer address segment, and the pattern includes a start command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied after loading of the block of data into the memory array.

25. The floating gate memory circuit of claim 15, wherein locations for data to be stored are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a page address segment and a page buffer address segment, and the pattern includes a load command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied during loading of the block of data into the memory array.

26. The floating gate memory circuit of claim 25, wherein the pattern includes changing the page address segment of the received address from the load command to the value within the address range while loading a last data segment in the sequence.

27. The floating gate memory circuit of claim 15, wherein the input/output circuitry receives a control signal establishing timing for the sequence of addresses and data segments, the command logic includes logic to detect a pulse in the control signal having a characteristic pulse width indicating that the block is loaded, and wherein the write control circuitry applies program voltages in response to either detection of the last segment in the block or detection of the pulse.

28. The floating gate memory circuit of claim 15, wherein the programming voltages applied to the floating gate cells cause Fowler-Nordheim tunneling in cells to be programmed.

29. The floating gate memory circuit of claim 15, wherein the programming voltages applied to the floating gate cells cause hot electron injection in cells to be programmed.

30. The floating gate memory of claim 15, wherein the pattern comprises an address transition in the sequence of addresses and data segments received at the input/output circuitry.

31. A method for storing a block of data consisting of less than or equal to a page in a floating gate memory device, comprising:

supplying a command which indicates an automatic program operation to the memory device;

after supplying the command, supplying a stream of addresses and segments of data, and storing the supplied segments in a page buffer;

monitoring the supplied stream of addresses and segments of data to detect a pattern in the supplied stream which signals an end of the block of data; and

after detection of the pattern, executing a program operation to store the block of data from the page buffer into the floating gate memory device.

32. The method of claim 31, wherein the pattern includes two matching addresses in sequence in the stream.

33. The method of claim 31, wherein the pattern includes a sequence of two matching addresses and two matching segments of data in the system.

34. The method of claim 31, wherein the pattern includes an address in the stream matching a prespecified command address.

35. The method of claim 31, wherein locations in the floating gate memory device for data to be stored are identified by the stream of addresses within an address range, the stream of addresses within the address range having a page address segment and a page buffer address segment, and the pattern includes a start command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied after loading the block of data into the floating gate memory device.

36. The method of claim 31, wherein locations in the floating gate memory device for data to be stored are identified by the stream of addresses within and address range, the stream of addresses within the address range having a page address segment and a page buffer segment, and the pattern includes a load command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied during loading of the block of data into the floating gate memory device, the pattern further including a change in the page address segment to a value within the address range.

37. The method of claim 36, wherein the pattern includes changing the page address segment of the received address from the load command to the value within the address range while loading a last data segment in the stream.

38. The method of claim 31, wherein the step of storing includes storing the block of data in parallel.

39. The method of claim 31, further including the step of automatically verifying the storing of the block of data into the floating gate memory device, and retrying the storing if an error is found.

40. The method of claim 31, wherein the pattern comprises an address transition in the stream of supplied addresses and data segments.