Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug

• US 5,780,323 A
• Filed: 11/12/1996
• Issued: 07/14/1998
• Est. Priority Date: 04/12/1990
• Status: Expired due to Fees

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Hawley, Frank W., McCollum, John L., Forouhi, Abdul R., Yen, Yeouchung
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/758,281
• Time in Patent Office: 609 Days
• Field of Search: 438/129, 438/130, 438/131, 438/631, 438/634, 438/636, 438/652, 438/653, 438/656, 438/657, 438/661, 438/633
• US Class Current: 438/131
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.

Claims

1. A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of:

a. disposing a first metallization layer on an insulating portion of the integrated circuit;

b. disposing an antifuse material layer over said first metallization layer;

c. disposing an etch-stop layer over said antifuse material layer;

d. patterning and etching said antifuse material layer;

e. disposing a dielectric layer over said etch-stop layer;

f. etching a via entirely through said dielectric layer to expose said etch-stop layer;

g. disposing a plug of a conductive material within said via;

h. disposing a second metallization layer over said dielectric layer and said plug and in electrical contact with said plug.

2. The method of claim 1 wherein step (g) is accomplished by means of chemical vapor deposition.

3. The method of claim 2 wherein tungsten is the material deposited by means of chemical vapor deposition.

4. The method of claim 1 wherein step (g) is accomplished by means of sputter deposition of a conductive metal.

5. A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of:

a. disposing a first metallization layer on an insulating portion of the integrated circuit;

b. disposing an antifuse material layer over said first metallization layer, said antifuse material layer including a first layer of amorphous silicon disposed on said first metallization layer and a second layer of an insulating material disposed on said first layer, said insulating material being a material other than amorphous silicon;

c. disposing an electrically conductive etch-stop layer over said antifuse material layer;

d. patterning and etching said antifuse material layer;

e. disposing a dielectric layer over said first amorphous silicon layer;

f. etching a via entirely through said dielectric layer to expose said etch-stop layer;

g. disposing an electrically conductive material in the form of a plug in said via to form an electrical path from said electrically conductive etch-stop layer through said dielectric layer; and

h. disposing a second metallization layer over and in electrical contact with said plug.

6. A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of:

a. disposing a first metallization layer on an insulating portion of the integrated circuit;

b. disposing an antifuse material layer over said first metallization layer;

c. disposing a first layer of amorphous silicon over said antifuse material layer;

d. patterning and etching said antifuse material layer;

e. disposing a dielectric layer over said first amorphous silicon layer;

f. etching a via entirely through said dielectric layer and partially into said first amorphous silicon layer;

g. disposing a layer of titanium over said via;

h. thermally reacting said layer of titanium and said first layer of amorphous silicon to form a region of electrically conductive titanium silicide in the vicinity of said via and extending vertically substantially entirely through said first amorphous silicon layer;

i. depositing a layer of an electrically conductive material in the form of a plug in said via substantially filling said via; and

j. disposing a second metallization layer over said dielectric layer and over and in electrical contact with said plug.

7. The method of claim 6 further comprising the step of depositing a barrier layer over said layer of titanium and under said plug.

8. The method of claim 7 wherein said barrier layer is a material selected from the group consisting of:

TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.

9. The method of claim 6 wherein step (b) comprises the sub-steps of:

i. disposing a first silicon nitride layer over said first metallization layer;

ii. disposing a second amorphous silicon layer over said first silicon nitride layer; and

iii. disposing a second silicon nitride layer over said second amorphous silicon layer.

10. The method of claim 9 wherein step (a) comprises the sub-steps of:

i. disposing a first barrier layer of a material selected from the group consisting of;

TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials;

ii. disposing a first layer of aluminum over said first barrier layer; and

iii. disposing a second barrier layer over said first layer of aluminum, said second barrier layer of a material selected from the group consisting of;

TiN, TiW, TiWN, W, TiC, WC and combinations of two or more of any of the foregoing materials.

11. The method of claim 6 wherein step (i) is accomplished by Chemical Vapor Deposition of a material selected from the group consisting of W and TiN.

12. A method of fabricating an antifuse disposed on an integrated circuit comprising the steps of:

a. disposing a first metallization layer on an insulating portion of the integrated circuit;

b. disposing an antifuse material layer over said first metallization layer, said antifuse material layer including a first layer of amorphous silicon disposed on said first metallization layer and a second layer of an insulating material disposed on said first layer of amorphous silicon, said second layer of an insulating material being a material other than amorphous silicon;

c. disposing a second layer of amorphous silicon over said antifuse material layer;

d. patterning and etching said antifuse material layer and said layer of amorphous silicon;

e. disposing a dielectric layer over said second amorphous silicon layer;

f. etching a via entirely through said dielectric layer and partially into said second amorphous silicon layer;

g. disposing a layer of Ti over said via and in contact with said second amorphous silicon layer;

h. thermally reacting said Ti and said second layer of amorphous silicon to form a region of electrically conductive titanium silicide in the vicinity of said via and extending vertically substantially entirely through said second layer of amorphous silicon;

i. disposing a plug of an electrically conductive material in said via and substantially filling said via; and

j. disposing a second metallization layer over and in electrical contact with said plug.

13. The method of claim 12 wherein said second layer of an insulating material includes silicon nitride.

14. The method of claim 12 wherein step (a) comprises the sub-steps of:

i. disposing a first barrier layer over an insulating portion of the integrated circuit;

ii. disposing a conductive metal layer over said first barrier layer; and

iii. disposing a second barrier layer over said conductive metal layer.

15. The method of claim 12 wherein step (i) comprises the sub-steps of:

i. disposing a barrier layer over said titanium layer; and

ii. CVD deposition of said electrically conductive material within said via.

16. The method of claim 12 wherein said electrically conductive material is tungsten.